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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 | // SPDX-License-Identifier: GPL-2.0+ /* * drivers/net/phy/qsemi.c * * Driver for Quality Semiconductor PHYs * * Author: Andy Fleming * * Copyright (c) 2004 Freescale Semiconductor, Inc. */ #include <linux/kernel.h> #include <linux/string.h> #include <linux/errno.h> #include <linux/unistd.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/spinlock.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/mii.h> #include <linux/ethtool.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/irq.h> #include <linux/uaccess.h> /* ------------------------------------------------------------------------- */ /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ /* register definitions */ #define MII_QS6612_MCR 17 /* Mode Control Register */ #define MII_QS6612_FTR 27 /* Factory Test Register */ #define MII_QS6612_MCO 28 /* Misc. Control Register */ #define MII_QS6612_ISR 29 /* Interrupt Source Register */ #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ #define MII_QS6612_IMR_INIT 0x003a #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ #define QS6612_PCR_AN_COMPLETE 0x1000 #define QS6612_PCR_RLBEN 0x0200 #define QS6612_PCR_DCREN 0x0100 #define QS6612_PCR_4B5BEN 0x0040 #define QS6612_PCR_TX_ISOLATE 0x0020 #define QS6612_PCR_MLT3_DIS 0x0002 #define QS6612_PCR_SCRM_DESCRM 0x0001 MODULE_DESCRIPTION("Quality Semiconductor PHY driver"); MODULE_AUTHOR("Andy Fleming"); MODULE_LICENSE("GPL"); /* Returns 0, unless there's a write error */ static int qs6612_config_init(struct phy_device *phydev) { /* The PHY powers up isolated on the RPX, * so send a command to allow operation. * XXX - My docs indicate this should be 0x0940 * ...or something. The current value sets three * reserved bits, bit 11, which specifies it should be * set to one, bit 10, which specifies it should be set * to 0, and bit 7, which doesn't specify. However, my * docs are preliminary, and I will leave it like this * until someone more knowledgable corrects me or it. * -- Andy Fleming */ return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); } static int qs6612_ack_interrupt(struct phy_device *phydev) { int err; err = phy_read(phydev, MII_QS6612_ISR); if (err < 0) return err; err = phy_read(phydev, MII_BMSR); if (err < 0) return err; err = phy_read(phydev, MII_EXPANSION); if (err < 0) return err; return 0; } static int qs6612_config_intr(struct phy_device *phydev) { int err; if (phydev->interrupts == PHY_INTERRUPT_ENABLED) err = phy_write(phydev, MII_QS6612_IMR, MII_QS6612_IMR_INIT); else err = phy_write(phydev, MII_QS6612_IMR, 0); return err; } static struct phy_driver qs6612_driver[] = { { .phy_id = 0x00181440, .name = "QS6612", .phy_id_mask = 0xfffffff0, /* PHY_BASIC_FEATURES */ .config_init = qs6612_config_init, .ack_interrupt = qs6612_ack_interrupt, .config_intr = qs6612_config_intr, } }; module_phy_driver(qs6612_driver); static struct mdio_device_id __maybe_unused qs6612_tbl[] = { { 0x00181440, 0xfffffff0 }, { } }; MODULE_DEVICE_TABLE(mdio, qs6612_tbl); |