Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 | /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" #include <dt-bindings/mfd/st-lpc.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/reset/stih407-resets.h> #include <dt-bindings/interrupt-controller/irq-st.h> / { #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; }; }; intc: interrupt-controller@08761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; scu@08760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; timer@08760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&arm_periph_clk>; }; l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x08762000 0x1000>; arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; arm-pmu { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; pwm_regulator: pwm-regulator { compatible = "pwm-regulator"; pwms = <&pwm1 3 8448>; regulator-name = "CPU_1V0_AVS"; regulator-min-microvolt = <784000>; regulator-max-microvolt = <1299000>; regulator-always-on; max-duty-cycle = <255>; status = "okay"; }; soc { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; compatible = "simple-bus"; restart { compatible = "st,stih407-restart"; st,syscfg = <&syscfg_sbc_reg>; status = "okay"; }; powerdown: powerdown-controller { compatible = "st,stih407-powerdown"; #reset-cells = <1>; }; softreset: softreset-controller { compatible = "st,stih407-softreset"; #reset-cells = <1>; }; picophyreset: picophyreset-controller { compatible = "st,stih407-picophyreset"; #reset-cells = <1>; }; syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; reg = <0x9620000 0x1000>; }; syscfg_front: front-syscfg@9280000 { compatible = "st,stih407-front-syscfg", "syscon"; reg = <0x9280000 0x1000>; }; syscfg_rear: rear-syscfg@9290000 { compatible = "st,stih407-rear-syscfg", "syscon"; reg = <0x9290000 0x1000>; }; syscfg_flash: flash-syscfg@92a0000 { compatible = "st,stih407-flash-syscfg", "syscon"; reg = <0x92a0000 0x1000>; }; syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { compatible = "st,stih407-sbc-reg-syscfg", "syscon"; reg = <0x9600000 0x1000>; }; syscfg_core: core-syscfg@92b0000 { compatible = "st,stih407-core-syscfg", "syscon"; reg = <0x92b0000 0x1000>; }; syscfg_lpm: lpm-syscfg@94b5100 { compatible = "st,stih407-lpm-syscfg", "syscon"; reg = <0x94b5100 0x1000>; }; irq-syscfg { compatible = "st,stih407-irq-syscfg"; st,syscfg = <&syscfg_core>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, <ST_IRQ_SYSCFG_DISABLED>; }; /* Display */ vtg_main: sti-vtg-main@8d02800 { compatible = "st,vtg"; reg = <0x8d02800 0x200>; interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; }; vtg_aux: sti-vtg-aux@8d00200 { compatible = "st,vtg"; reg = <0x8d00200 0x100>; interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; }; serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial0>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; serial@9831000 { compatible = "st,asc"; reg = <0x9831000 0x2c>; interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; serial@9832000 { compatible = "st,asc"; reg = <0x9832000 0x2c>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; /* SBC_ASC0 - UART10 */ sbc_serial0: serial@9530000 { compatible = "st,asc"; reg = <0x9530000 0x2c>; interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial0>; clocks = <&clk_sysin>; status = "disabled"; }; serial@9531000 { compatible = "st,asc"; reg = <0x9531000 0x2c>; interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&clk_sysin>; status = "disabled"; }; i2c@9840000 { compatible = "st,comms-ssc4-i2c"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0x9840000 0x110>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; status = "disabled"; }; i2c@9841000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9841000 0x110>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; i2c@9842000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9842000 0x110>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; i2c@9843000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9843000 0x110>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_default>; status = "disabled"; }; i2c@9844000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9844000 0x110>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4_default>; status = "disabled"; }; i2c@9845000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9845000 0x110>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c5_default>; status = "disabled"; }; /* SSCs on SBC */ i2c@9540000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9540000 0x110>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; i2c@9541000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9541000 0x110>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; usb2_picophy0: phy1 { compatible = "st,stih407-usb2-phy"; #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, <&picophyreset STIH407_PICOPHY2_RESET>; reset-names = "global", "port"; }; miphy28lp_phy: miphy28lp@9b22000 { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; ranges; phy_port0: port@9b22000 { reg = <0x9b22000 0xff>, <0x9b09000 0xff>, <0x9b04000 0xff>; reg-names = "sata-up", "pcie-up", "pipew"; st,syscfg = <0x114 0x818 0xe0 0xec>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY0_SOFTRESET>; }; phy_port1: port@9b2a000 { reg = <0x9b2a000 0xff>, <0x9b19000 0xff>, <0x9b14000 0xff>; reg-names = "sata-up", "pcie-up", "pipew"; st,syscfg = <0x118 0x81c 0xe4 0xf0>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY1_SOFTRESET>; }; phy_port2: port@8f95000 { reg = <0x8f95000 0xff>, <0x8f90000 0xff>; reg-names = "pipew", "usb3-up"; st,syscfg = <0x11c 0x820>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY2_SOFTRESET>; }; }; spi@9840000 { compatible = "st,comms-ssc4-spi"; reg = <0x9840000 0x110>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; pinctrl-0 = <&pinctrl_spi0_default>; pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi@9841000 { compatible = "st,comms-ssc4-spi"; reg = <0x9841000 0x110>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; status = "disabled"; }; spi@9842000 { compatible = "st,comms-ssc4-spi"; reg = <0x9842000 0x110>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2_default>; status = "disabled"; }; spi@9843000 { compatible = "st,comms-ssc4-spi"; reg = <0x9843000 0x110>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi3_default>; status = "disabled"; }; spi@9844000 { compatible = "st,comms-ssc4-spi"; reg = <0x9844000 0x110>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4_default>; status = "disabled"; }; /* SBC SSC */ spi@9540000 { compatible = "st,comms-ssc4-spi"; reg = <0x9540000 0x110>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi10_default>; status = "disabled"; }; spi@9541000 { compatible = "st,comms-ssc4-spi"; reg = <0x9541000 0x110>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi11_default>; status = "disabled"; }; spi@9542000 { compatible = "st,comms-ssc4-spi"; reg = <0x9542000 0x110>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi12_default>; status = "disabled"; }; mmc0: sdhci@09060000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; reg-names = "mmc", "top-mmc-delay"; interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0>; clock-names = "mmc"; clocks = <&clk_s_c0_flexgen CLK_MMC_0>; bus-width = <8>; non-removable; }; mmc1: sdhci@09080000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09080000 0x7ff>; reg-names = "mmc"; interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd1>; clock-names = "mmc"; clocks = <&clk_s_c0_flexgen CLK_MMC_1>; resets = <&softreset STIH407_MMC1_SOFTRESET>; bus-width = <4>; }; /* Watchdog and Real-Time Clock */ lpc@8787000 { compatible = "st,stih407-lpc"; reg = <0x8787000 0x1000>; interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; clocks = <&clk_s_d3_flexgen CLK_LPC_0>; timeout-sec = <120>; st,syscfg = <&syscfg_core>; st,lpc-mode = <ST_LPC_MODE_WDT>; }; lpc@8788000 { compatible = "st,stih407-lpc"; reg = <0x8788000 0x1000>; interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; clocks = <&clk_s_d3_flexgen CLK_LPC_1>; st,lpc-mode = <ST_LPC_MODE_RTC>; }; sata0: sata@9b20000 { compatible = "st,ahci"; reg = <0x9b20000 0x1000>; interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; interrupt-names = "hostc"; phys = <&phy_port0 PHY_TYPE_SATA>; phy-names = "ahci_phy"; resets = <&powerdown STIH407_SATA0_POWERDOWN>, <&softreset STIH407_SATA0_SOFTRESET>, <&softreset STIH407_SATA0_PWR_SOFTRESET>; reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; status = "disabled"; }; sata1: sata@9b28000 { compatible = "st,ahci"; reg = <0x9b28000 0x1000>; interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; interrupt-names = "hostc"; phys = <&phy_port1 PHY_TYPE_SATA>; phy-names = "ahci_phy"; resets = <&powerdown STIH407_SATA1_POWERDOWN>, <&softreset STIH407_SATA1_SOFTRESET>, <&softreset STIH407_SATA1_PWR_SOFTRESET>; reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; status = "disabled"; }; st_dwc3: dwc3@8f94000 { compatible = "st,stih407-dwc3"; reg = <0x08f94000 0x1000>, <0x110 0x4>; reg-names = "reg-glue", "syscfg-reg"; st,syscfg = <&syscfg_core>; resets = <&powerdown STIH407_USB3_POWERDOWN>, <&softreset STIH407_MIPHY2_SOFTRESET>; reset-names = "powerdown", "softreset"; #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; ranges; status = "disabled"; dwc3: dwc3@9900000 { compatible = "snps,dwc3"; reg = <0x09900000 0x100000>; interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; dr_mode = "host"; phy-names = "usb2-phy", "usb3-phy"; phys = <&usb2_picophy0>, <&phy_port2 PHY_TYPE_USB3>; }; }; /* COMMS PWM Module */ pwm0: pwm@9810000 { compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9810000 0x68>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default>; clock-names = "pwm"; clocks = <&clk_sysin>; st,pwm-num-chan = <1>; status = "disabled"; }; /* SBC PWM Module */ pwm1: pwm@9510000 { compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9510000 0x68>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1_chan0_default &pinctrl_pwm1_chan1_default &pinctrl_pwm1_chan2_default &pinctrl_pwm1_chan3_default>; clock-names = "pwm"; clocks = <&clk_sysin>; st,pwm-num-chan = <4>; status = "disabled"; }; rng10: rng@08a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; rng11: rng@08a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; ethernet0: dwmac@9630000 { device_type = "network"; status = "disabled"; compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; reg = <0x9630000 0x8000>, <0x80 0x4>; reg-names = "stmmaceth", "sti-ethconf"; st,syscon = <&syscfg_sbc_reg 0x80>; st,gmac_en; resets = <&softreset STIH407_ETH1_SOFTRESET>; reset-names = "stmmaceth"; interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, <GIC_SPI 99 IRQ_TYPE_NONE>; interrupt-names = "macirq", "eth_wake_irq"; /* DMA Bus Mode */ snps,pbl = <8>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii1>; clock-names = "stmmaceth", "sti-ethclk"; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_ETH_PHY>; }; rng10: rng@08a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; rng11: rng@08a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; }; }; |