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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 | /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" #include <dt-bindings/reset-controller/stih407-resets.h> / { #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; }; }; intc: interrupt-controller@08761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; scu@08760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; timer@08760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&arm_periph_clk>; }; l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x08762000 0x1000>; arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; soc { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; compatible = "simple-bus"; powerdown: powerdown-controller { compatible = "st,stih407-powerdown"; #reset-cells = <1>; }; softreset: softreset-controller { compatible = "st,stih407-softreset"; #reset-cells = <1>; }; picophyreset: picophyreset-controller { compatible = "st,stih407-picophyreset"; #reset-cells = <1>; }; syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; reg = <0x9620000 0x1000>; }; syscfg_front: front-syscfg@9280000 { compatible = "st,stih407-front-syscfg", "syscon"; reg = <0x9280000 0x1000>; }; syscfg_rear: rear-syscfg@9290000 { compatible = "st,stih407-rear-syscfg", "syscon"; reg = <0x9290000 0x1000>; }; syscfg_flash: flash-syscfg@92a0000 { compatible = "st,stih407-flash-syscfg", "syscon"; reg = <0x92a0000 0x1000>; }; syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { compatible = "st,stih407-sbc-reg-syscfg", "syscon"; reg = <0x9600000 0x1000>; }; syscfg_core: core-syscfg@92b0000 { compatible = "st,stih407-core-syscfg", "syscon"; reg = <0x92b0000 0x1000>; }; syscfg_lpm: lpm-syscfg@94b5100 { compatible = "st,stih407-lpm-syscfg", "syscon"; reg = <0x94b5100 0x1000>; }; serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial0>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; serial@9831000 { compatible = "st,asc"; reg = <0x9831000 0x2c>; interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; serial@9832000 { compatible = "st,asc"; reg = <0x9832000 0x2c>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; /* SBC_ASC0 - UART10 */ sbc_serial0: serial@9530000 { compatible = "st,asc"; reg = <0x9530000 0x2c>; interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial0>; clocks = <&clk_sysin>; status = "disabled"; }; serial@9531000 { compatible = "st,asc"; reg = <0x9531000 0x2c>; interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&clk_sysin>; status = "disabled"; }; i2c@9840000 { compatible = "st,comms-ssc4-i2c"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0x9840000 0x110>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; status = "disabled"; }; i2c@9841000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9841000 0x110>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; i2c@9842000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9842000 0x110>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; i2c@9843000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9843000 0x110>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_default>; status = "disabled"; }; i2c@9844000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9844000 0x110>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4_default>; status = "disabled"; }; i2c@9845000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9845000 0x110>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c5_default>; status = "disabled"; }; /* SSCs on SBC */ i2c@9540000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9540000 0x110>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; i2c@9541000 { compatible = "st,comms-ssc4-i2c"; reg = <0x9541000 0x110>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; usb2_picophy0: phy1 { compatible = "st,stih407-usb2-phy"; #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, <&picophyreset STIH407_PICOPHY0_RESET>; reset-names = "global", "port"; }; miphy28lp_phy: miphy28lp@9b22000 { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; ranges; phy_port0: port@9b22000 { reg = <0x9b22000 0xff>, <0x9b09000 0xff>, <0x9b04000 0xff>; reg-names = "sata-up", "pcie-up", "pipew"; st,syscfg = <0x114 0x818 0xe0 0xec>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY0_SOFTRESET>; }; phy_port1: port@9b2a000 { reg = <0x9b2a000 0xff>, <0x9b19000 0xff>, <0x9b14000 0xff>; reg-names = "sata-up", "pcie-up", "pipew"; st,syscfg = <0x118 0x81c 0xe4 0xf0>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY1_SOFTRESET>; }; phy_port2: port@8f95000 { reg = <0x8f95000 0xff>, <0x8f90000 0xff>; reg-names = "pipew", "usb3-up"; st,syscfg = <0x11c 0x820>; #phy-cells = <1>; reset-names = "miphy-sw-rst"; resets = <&softreset STIH407_MIPHY2_SOFTRESET>; }; }; }; }; |