Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 | /** * dwc3-omap.c - OMAP Specific Glue layer * * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions, and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The names of the above-listed copyright holders may not be used * to endorse or promote products derived from this software without * specific prior written permission. * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2, as published by the Free * Software Foundation. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/platform_device.h> #include <linux/platform_data/dwc3-omap.h> #include <linux/dma-mapping.h> #include <linux/ioport.h> #include <linux/io.h> #include <linux/of.h> #include "core.h" #include "io.h" /* * All these registers belong to OMAP's Wrapper around the * DesignWare USB3 Core. */ #define USBOTGSS_REVISION 0x0000 #define USBOTGSS_SYSCONFIG 0x0010 #define USBOTGSS_IRQ_EOI 0x0020 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 #define USBOTGSS_IRQSTATUS_0 0x0028 #define USBOTGSS_IRQENABLE_SET_0 0x002c #define USBOTGSS_IRQENABLE_CLR_0 0x0030 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034 #define USBOTGSS_IRQSTATUS_1 0x0038 #define USBOTGSS_IRQENABLE_SET_1 0x003c #define USBOTGSS_IRQENABLE_CLR_1 0x0040 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 #define USBOTGSS_MMRAM_OFFSET 0x0100 #define USBOTGSS_FLADJ 0x0104 #define USBOTGSS_DEBUG_CFG 0x0108 #define USBOTGSS_DEBUG_DATA 0x010c /* SYSCONFIG REGISTER */ #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4) #define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0 #define USBOTGSS_STANDBYMODE_NO_STANDBY 1 #define USBOTGSS_STANDBYMODE_SMART_STANDBY 2 #define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3 #define USBOTGSS_STANDBYMODE_MASK (0x03 << 4) #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2) #define USBOTGSS_IDLEMODE_FORCE_IDLE 0 #define USBOTGSS_IDLEMODE_NO_IDLE 1 #define USBOTGSS_IDLEMODE_SMART_IDLE 2 #define USBOTGSS_IDLEMODE_SMART_WAKEUP 3 #define USBOTGSS_IDLEMODE_MASK (0x03 << 2) /* IRQ_EOI REGISTER */ #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) /* IRQS0 BITS */ #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) /* IRQ1 BITS */ #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17) #define USBOTGSS_IRQ1_OEVT (1 << 16) #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13) #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12) #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11) #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8) #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5) #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4) #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3) #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0) /* UTMI_OTG_CTRL REGISTER */ #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) /* UTMI_OTG_STATUS REGISTER */ #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) struct dwc3_omap { /* device lock */ spinlock_t lock; struct platform_device *dwc3; struct device *dev; int irq; void __iomem *base; void *context; u32 resource_size; u32 dma_status:1; }; static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) { struct dwc3_omap *omap = _omap; u32 reg; spin_lock(&omap->lock); reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1); if (reg & USBOTGSS_IRQ1_DMADISABLECLR) { dev_dbg(omap->dev, "DMA Disable was Cleared\n"); omap->dma_status = false; } if (reg & USBOTGSS_IRQ1_OEVT) dev_dbg(omap->dev, "OTG Event\n"); if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) dev_dbg(omap->dev, "DRVVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) dev_dbg(omap->dev, "CHRGVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) dev_dbg(omap->dev, "IDPULLUP Rise\n"); if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) dev_dbg(omap->dev, "DRVVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) dev_dbg(omap->dev, "CHRGVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) dev_dbg(omap->dev, "IDPULLUP Fall\n"); dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg); reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0); dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg); spin_unlock(&omap->lock); return IRQ_HANDLED; } static int __devinit dwc3_omap_probe(struct platform_device *pdev) { struct dwc3_omap_data *pdata = pdev->dev.platform_data; struct device_node *node = pdev->dev.of_node; struct platform_device *dwc3; struct dwc3_omap *omap; struct resource *res; struct device *dev = &pdev->dev; int devid; int size; int ret = -ENOMEM; int irq; const u32 *utmi_mode; u32 reg; void __iomem *base; void *context; omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); if (!omap) { dev_err(dev, "not enough memory\n"); return -ENOMEM; } platform_set_drvdata(pdev, omap); irq = platform_get_irq(pdev, 1); if (irq < 0) { dev_err(dev, "missing IRQ resource\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) { dev_err(dev, "missing memory base resource\n"); return -EINVAL; } base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) { dev_err(dev, "ioremap failed\n"); return -ENOMEM; } devid = dwc3_get_device_id(); if (devid < 0) return -ENODEV; dwc3 = platform_device_alloc("dwc3", devid); if (!dwc3) { dev_err(dev, "couldn't allocate dwc3 device\n"); goto err1; } context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL); if (!context) { dev_err(dev, "couldn't allocate dwc3 context memory\n"); goto err2; } spin_lock_init(&omap->lock); dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask); dwc3->dev.parent = dev; dwc3->dev.dma_mask = dev->dma_mask; dwc3->dev.dma_parms = dev->dma_parms; omap->resource_size = resource_size(res); omap->context = context; omap->dev = dev; omap->irq = irq; omap->base = base; omap->dwc3 = dwc3; reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); utmi_mode = of_get_property(node, "utmi-mode", &size); if (utmi_mode && size == sizeof(*utmi_mode)) { reg |= *utmi_mode; } else { if (!pdata) { dev_dbg(dev, "missing platform data\n"); } else { switch (pdata->utmi_mode) { case DWC3_OMAP_UTMI_MODE_SW: reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; case DWC3_OMAP_UTMI_MODE_HW: reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; default: dev_dbg(dev, "UNKNOWN utmi mode %d\n", pdata->utmi_mode); } } } dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); /* check the DMA Status */ reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG); omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); /* Set No-Idle and No-Standby */ reg &= ~(USBOTGSS_STANDBYMODE_MASK | USBOTGSS_IDLEMODE_MASK); reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY) | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE)); dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg); ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, "dwc3-omap", omap); if (ret) { dev_err(dev, "failed to request IRQ #%d --> %d\n", omap->irq, ret); goto err2; } /* enable all IRQs */ reg = USBOTGSS_IRQO_COREIRQ_ST; dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); reg = (USBOTGSS_IRQ1_OEVT | USBOTGSS_IRQ1_DRVVBUS_RISE | USBOTGSS_IRQ1_CHRGVBUS_RISE | USBOTGSS_IRQ1_DISCHRGVBUS_RISE | USBOTGSS_IRQ1_IDPULLUP_RISE | USBOTGSS_IRQ1_DRVVBUS_FALL | USBOTGSS_IRQ1_CHRGVBUS_FALL | USBOTGSS_IRQ1_DISCHRGVBUS_FALL | USBOTGSS_IRQ1_IDPULLUP_FALL); dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); ret = platform_device_add_resources(dwc3, pdev->resource, pdev->num_resources); if (ret) { dev_err(dev, "couldn't add resources to dwc3 device\n"); goto err2; } ret = platform_device_add(dwc3); if (ret) { dev_err(dev, "failed to register dwc3 device\n"); goto err2; } return 0; err2: platform_device_put(dwc3); err1: dwc3_put_device_id(devid); return ret; } static int __devexit dwc3_omap_remove(struct platform_device *pdev) { struct dwc3_omap *omap = platform_get_drvdata(pdev); platform_device_unregister(omap->dwc3); dwc3_put_device_id(omap->dwc3->id); return 0; } static const struct of_device_id of_dwc3_matach[] = { { "ti,dwc3", }, { }, }; MODULE_DEVICE_TABLE(of, of_dwc3_matach); static struct platform_driver dwc3_omap_driver = { .probe = dwc3_omap_probe, .remove = __devexit_p(dwc3_omap_remove), .driver = { .name = "omap-dwc3", .of_match_table = of_dwc3_matach, }, }; module_platform_driver(dwc3_omap_driver); MODULE_ALIAS("platform:omap-dwc3"); MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); MODULE_LICENSE("Dual BSD/GPL"); MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); |