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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 | /* * arch/xtensa/mm/misc.S * * Miscellaneous assembly functions. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2007 Tensilica Inc. * * Chris Zankel <chris@zankel.net> */ #include <linux/linkage.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/asmmacro.h> #include <asm/cacheasm.h> #include <asm/tlbflush.h> /* * clear_page and clear_user_page are the same for non-cache-aliased configs. * * clear_page (unsigned long page) * a2 */ ENTRY(clear_page) entry a1, 16 movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 s32i a3, a2, 0 s32i a3, a2, 4 s32i a3, a2, 8 s32i a3, a2, 12 s32i a3, a2, 16 s32i a3, a2, 20 s32i a3, a2, 24 s32i a3, a2, 28 __endla a2, a7, 32 retw /* * copy_page and copy_user_page are the same for non-cache-aliased configs. * * copy_page (void *to, void *from) * a2 a3 */ ENTRY(copy_page) entry a1, 16 __loopi a2, a4, PAGE_SIZE, 32 l32i a8, a3, 0 l32i a9, a3, 4 s32i a8, a2, 0 s32i a9, a2, 4 l32i a8, a3, 8 l32i a9, a3, 12 s32i a8, a2, 8 s32i a9, a2, 12 l32i a8, a3, 16 l32i a9, a3, 20 s32i a8, a2, 16 s32i a9, a2, 20 l32i a8, a3, 24 l32i a9, a3, 28 s32i a8, a2, 24 s32i a9, a2, 28 addi a2, a2, 32 addi a3, a3, 32 __endl a2, a4 retw /* * If we have to deal with cache aliasing, we use temporary memory mappings * to ensure that the source and destination pages have the same color as * the virtual address. We use way 0 and 1 for temporary mappings in such cases. * * The temporary DTLB entries shouldn't be flushed by interrupts, but are * flushed by preemptive task switches. Special code in the * fast_second_level_miss handler re-established the temporary mapping. * It requires that the PPNs for the destination and source addresses are * in a6, and a7, respectively. */ /* TLB miss exceptions are treated special in the following region */ ENTRY(__tlbtemp_mapping_start) #if (DCACHE_WAY_SIZE > PAGE_SIZE) /* * clear_user_page (void *addr, unsigned long vaddr, struct page *page) * a2 a3 a4 */ ENTRY(clear_user_page) entry a1, 32 /* Mark page dirty and determine alias. */ movi a7, (1 << PG_ARCH_1) l32i a5, a4, PAGE_FLAGS xor a6, a2, a3 extui a3, a3, PAGE_SHIFT, DCACHE_ALIAS_ORDER extui a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER or a5, a5, a7 slli a3, a3, PAGE_SHIFT s32i a5, a4, PAGE_FLAGS /* Skip setting up a temporary DTLB if not aliased. */ beqz a6, 1f /* Invalidate kernel page. */ mov a10, a2 call8 __invalidate_dcache_page /* Setup a temporary DTLB with the color of the VPN */ movi a4, -PAGE_OFFSET + (PAGE_KERNEL | _PAGE_HW_WRITE) movi a5, TLBTEMP_BASE_1 # virt add a6, a2, a4 # ppn add a2, a5, a3 # add 'color' wdtlb a6, a2 dsync 1: movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 s32i a3, a2, 0 s32i a3, a2, 4 s32i a3, a2, 8 s32i a3, a2, 12 s32i a3, a2, 16 s32i a3, a2, 20 s32i a3, a2, 24 s32i a3, a2, 28 __endla a2, a7, 32 bnez a6, 1f retw /* We need to invalidate the temporary idtlb entry, if any. */ 1: addi a2, a2, -PAGE_SIZE idtlb a2 dsync retw /* * copy_page_user (void *to, void *from, unsigned long vaddr, struct page *page) * a2 a3 a4 a5 */ ENTRY(copy_user_page) entry a1, 32 /* Mark page dirty and determine alias for destination. */ movi a8, (1 << PG_ARCH_1) l32i a9, a5, PAGE_FLAGS xor a6, a2, a4 xor a7, a3, a4 extui a4, a4, PAGE_SHIFT, DCACHE_ALIAS_ORDER extui a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER extui a7, a7, PAGE_SHIFT, DCACHE_ALIAS_ORDER or a9, a9, a8 slli a4, a4, PAGE_SHIFT s32i a9, a5, PAGE_FLAGS movi a5, -PAGE_OFFSET + (PAGE_KERNEL | _PAGE_HW_WRITE) beqz a6, 1f /* Invalidate dcache */ mov a10, a2 call8 __invalidate_dcache_page /* Setup a temporary DTLB with a matching color. */ movi a8, TLBTEMP_BASE_1 # base add a6, a2, a5 # ppn add a2, a8, a4 # add 'color' wdtlb a6, a2 dsync /* Skip setting up a temporary DTLB for destination if not aliased. */ 1: beqz a7, 1f /* Setup a temporary DTLB with a matching color. */ movi a8, TLBTEMP_BASE_2 # base add a7, a3, a5 # ppn add a3, a8, a4 addi a8, a3, 1 # way1 wdtlb a7, a8 dsync 1: __loopi a2, a4, PAGE_SIZE, 32 l32i a8, a3, 0 l32i a9, a3, 4 s32i a8, a2, 0 s32i a9, a2, 4 l32i a8, a3, 8 l32i a9, a3, 12 s32i a8, a2, 8 s32i a9, a2, 12 l32i a8, a3, 16 l32i a9, a3, 20 s32i a8, a2, 16 s32i a9, a2, 20 l32i a8, a3, 24 l32i a9, a3, 28 s32i a8, a2, 24 s32i a9, a2, 28 addi a2, a2, 32 addi a3, a3, 32 __endl a2, a4 /* We need to invalidate any temporary mapping! */ bnez a6, 1f bnez a7, 2f retw 1: addi a2, a2, -PAGE_SIZE idtlb a2 dsync bnez a7, 2f retw 2: addi a3, a3, -PAGE_SIZE+1 idtlb a3 dsync retw #endif #if (DCACHE_WAY_SIZE > PAGE_SIZE) /* * void __flush_invalidate_dcache_page_alias (addr, phys) * a2 a3 */ ENTRY(__flush_invalidate_dcache_page_alias) entry sp, 16 movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) mov a4, a2 wdtlb a6, a2 dsync ___flush_invalidate_dcache_page a2 a3 idtlb a4 dsync retw #endif ENTRY(__tlbtemp_mapping_itlb) #if (ICACHE_WAY_SIZE > PAGE_SIZE) ENTRY(__invalidate_icache_page_alias) entry sp, 16 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) mov a4, a2 witlb a6, a2 isync ___invalidate_icache_page a2 a3 iitlb a4 isync retw #endif /* End of special treatment in tlb miss exception */ ENTRY(__tlbtemp_mapping_end) /* * void __invalidate_icache_page(ulong start) */ ENTRY(__invalidate_icache_page) entry sp, 16 ___invalidate_icache_page a2 a3 isync retw /* * void __invalidate_dcache_page(ulong start) */ ENTRY(__invalidate_dcache_page) entry sp, 16 ___invalidate_dcache_page a2 a3 dsync retw /* * void __flush_invalidate_dcache_page(ulong start) */ ENTRY(__flush_invalidate_dcache_page) entry sp, 16 ___flush_invalidate_dcache_page a2 a3 dsync retw /* * void __flush_dcache_page(ulong start) */ ENTRY(__flush_dcache_page) entry sp, 16 ___flush_dcache_page a2 a3 dsync retw /* * void __invalidate_icache_range(ulong start, ulong size) */ ENTRY(__invalidate_icache_range) entry sp, 16 ___invalidate_icache_range a2 a3 a4 isync retw /* * void __flush_invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__flush_invalidate_dcache_range) entry sp, 16 ___flush_invalidate_dcache_range a2 a3 a4 dsync retw /* * void _flush_dcache_range(ulong start, ulong size) */ ENTRY(__flush_dcache_range) entry sp, 16 ___flush_dcache_range a2 a3 a4 dsync retw /* * void _invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__invalidate_dcache_range) entry sp, 16 ___invalidate_dcache_range a2 a3 a4 retw /* * void _invalidate_icache_all(void) */ ENTRY(__invalidate_icache_all) entry sp, 16 ___invalidate_icache_all a2 a3 isync retw /* * void _flush_invalidate_dcache_all(void) */ ENTRY(__flush_invalidate_dcache_all) entry sp, 16 ___flush_invalidate_dcache_all a2 a3 dsync retw /* * void _invalidate_dcache_all(void) */ ENTRY(__invalidate_dcache_all) entry sp, 16 ___invalidate_dcache_all a2 a3 dsync retw |