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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 | /* * arch/xtensa/mm/misc.S * * Miscellaneous assembly functions. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2005 Tensilica Inc. * * Chris Zankel <chris@zankel.net> */ /* Note: we might want to implement some of the loops as zero-overhead-loops, * where applicable and if supported by the processor. */ #include <linux/linkage.h> #include <asm/page.h> #include <asm/pgtable.h> #include <xtensa/cacheasm.h> #include <xtensa/cacheattrasm.h> /* clear_page (page) */ ENTRY(clear_page) entry a1, 16 addi a4, a2, PAGE_SIZE movi a3, 0 1: s32i a3, a2, 0 s32i a3, a2, 4 s32i a3, a2, 8 s32i a3, a2, 12 s32i a3, a2, 16 s32i a3, a2, 20 s32i a3, a2, 24 s32i a3, a2, 28 addi a2, a2, 32 blt a2, a4, 1b retw /* * copy_page (void *to, void *from) * a2 a3 */ ENTRY(copy_page) entry a1, 16 addi a4, a2, PAGE_SIZE 1: l32i a5, a3, 0 l32i a6, a3, 4 l32i a7, a3, 8 s32i a5, a2, 0 s32i a6, a2, 4 s32i a7, a2, 8 l32i a5, a3, 12 l32i a6, a3, 16 l32i a7, a3, 20 s32i a5, a2, 12 s32i a6, a2, 16 s32i a7, a2, 20 l32i a5, a3, 24 l32i a6, a3, 28 s32i a5, a2, 24 s32i a6, a2, 28 addi a2, a2, 32 addi a3, a3, 32 blt a2, a4, 1b retw /* * void __flush_invalidate_cache_all(void) */ ENTRY(__flush_invalidate_cache_all) entry sp, 16 dcache_writeback_inv_all a2, a3 icache_invalidate_all a2, a3 retw /* * void __invalidate_icache_all(void) */ ENTRY(__invalidate_icache_all) entry sp, 16 icache_invalidate_all a2, a3 retw /* * void __flush_invalidate_dcache_all(void) */ ENTRY(__flush_invalidate_dcache_all) entry sp, 16 dcache_writeback_inv_all a2, a3 retw /* * void __flush_invalidate_cache_range(ulong start, ulong size) */ ENTRY(__flush_invalidate_cache_range) entry sp, 16 mov a4, a2 mov a5, a3 dcache_writeback_inv_region a4, a5, a6 icache_invalidate_region a2, a3, a4 retw /* * void __invalidate_icache_page(ulong start) */ ENTRY(__invalidate_icache_page) entry sp, 16 movi a3, PAGE_SIZE icache_invalidate_region a2, a3, a4 retw /* * void __invalidate_dcache_page(ulong start) */ ENTRY(__invalidate_dcache_page) entry sp, 16 movi a3, PAGE_SIZE dcache_invalidate_region a2, a3, a4 retw /* * void __invalidate_icache_range(ulong start, ulong size) */ ENTRY(__invalidate_icache_range) entry sp, 16 icache_invalidate_region a2, a3, a4 retw /* * void __invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__invalidate_dcache_range) entry sp, 16 dcache_invalidate_region a2, a3, a4 retw /* * void __flush_dcache_page(ulong start) */ ENTRY(__flush_dcache_page) entry sp, 16 movi a3, PAGE_SIZE dcache_writeback_region a2, a3, a4 retw /* * void __flush_invalidate_dcache_page(ulong start) */ ENTRY(__flush_invalidate_dcache_page) entry sp, 16 movi a3, PAGE_SIZE dcache_writeback_inv_region a2, a3, a4 retw /* * void __flush_invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__flush_invalidate_dcache_range) entry sp, 16 dcache_writeback_inv_region a2, a3, a4 retw /* * void __invalidate_dcache_all(void) */ ENTRY(__invalidate_dcache_all) entry sp, 16 dcache_invalidate_all a2, a3 retw /* * void __flush_invalidate_dcache_page_phys(ulong start) */ ENTRY(__flush_invalidate_dcache_page_phys) entry sp, 16 movi a3, XCHAL_DCACHE_SIZE movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_DCACHE_LINESIZE ldct a6, a3 dsync and a6, a6, a4 beq a6, a2, 2f bgeui a3, 2, 1b retw 2: diwbi a3, 0 bgeui a3, 2, 1b retw ENTRY(check_dcache_low0) entry sp, 16 movi a3, XCHAL_DCACHE_SIZE / 4 movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_DCACHE_LINESIZE ldct a6, a3 dsync and a6, a6, a4 beq a6, a2, 2f bgeui a3, 2, 1b retw 2: j 2b ENTRY(check_dcache_high0) entry sp, 16 movi a5, XCHAL_DCACHE_SIZE / 4 movi a3, XCHAL_DCACHE_SIZE / 2 movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_DCACHE_LINESIZE addi a5, a5, -XCHAL_DCACHE_LINESIZE ldct a6, a3 dsync and a6, a6, a4 beq a6, a2, 2f bgeui a5, 2, 1b retw 2: j 2b ENTRY(check_dcache_low1) entry sp, 16 movi a5, XCHAL_DCACHE_SIZE / 4 movi a3, XCHAL_DCACHE_SIZE * 3 / 4 movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_DCACHE_LINESIZE addi a5, a5, -XCHAL_DCACHE_LINESIZE ldct a6, a3 dsync and a6, a6, a4 beq a6, a2, 2f bgeui a5, 2, 1b retw 2: j 2b ENTRY(check_dcache_high1) entry sp, 16 movi a5, XCHAL_DCACHE_SIZE / 4 movi a3, XCHAL_DCACHE_SIZE movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_DCACHE_LINESIZE addi a5, a5, -XCHAL_DCACHE_LINESIZE ldct a6, a3 dsync and a6, a6, a4 beq a6, a2, 2f bgeui a5, 2, 1b retw 2: j 2b /* * void __invalidate_icache_page_phys(ulong start) */ ENTRY(__invalidate_icache_page_phys) entry sp, 16 movi a3, XCHAL_ICACHE_SIZE movi a4, PAGE_MASK | 1 addi a2, a2, 1 1: addi a3, a3, -XCHAL_ICACHE_LINESIZE lict a6, a3 isync and a6, a6, a4 beq a6, a2, 2f bgeui a3, 2, 1b retw 2: iii a3, 0 bgeui a3, 2, 1b retw #if 0 movi a3, XCHAL_DCACHE_WAYS - 1 movi a4, PAGE_SIZE 1: mov a5, a2 add a6, a2, a4 2: diwbi a5, 0 diwbi a5, XCHAL_DCACHE_LINESIZE diwbi a5, XCHAL_DCACHE_LINESIZE * 2 diwbi a5, XCHAL_DCACHE_LINESIZE * 3 addi a5, a5, XCHAL_DCACHE_LINESIZE * 4 blt a5, a6, 2b addi a3, a3, -1 addi a2, a2, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS bgez a3, 1b retw ENTRY(__invalidate_icache_page_index) entry sp, 16 movi a3, XCHAL_ICACHE_WAYS - 1 movi a4, PAGE_SIZE 1: mov a5, a2 add a6, a2, a4 2: iii a5, 0 iii a5, XCHAL_ICACHE_LINESIZE iii a5, XCHAL_ICACHE_LINESIZE * 2 iii a5, XCHAL_ICACHE_LINESIZE * 3 addi a5, a5, XCHAL_ICACHE_LINESIZE * 4 blt a5, a6, 2b addi a3, a3, -1 addi a2, a2, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS bgez a3, 2b retw #endif |