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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 | /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Inline assembly cache operations. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) */ #ifndef _ASM_R4KCACHE_H #define _ASM_R4KCACHE_H #include <asm/asm.h> #include <asm/cacheops.h> /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: * * - The MIPS32 and MIPS64 specs permit an implementation to directly derive * the index bits from the virtual address. This breaks with tradition * set by the R4000. To keep unpleasant surprises from happening we pick * an address in KSEG0 / CKSEG0. * - We need a properly sign extended address for 64-bit code. To get away * without ifdefs we let the compiler do it by a type cast. */ #define INDEX_BASE CKSEG0 #define cache_op(op,addr) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3\n\t \n" \ " cache %0, %1 \n" \ " .set pop \n" \ : \ : "i" (op), "m" (*(unsigned char *)(addr))) static inline void flush_icache_line_indexed(unsigned long addr) { cache_op(Index_Invalidate_I, addr); } static inline void flush_dcache_line_indexed(unsigned long addr) { cache_op(Index_Writeback_Inv_D, addr); } static inline void flush_scache_line_indexed(unsigned long addr) { cache_op(Index_Writeback_Inv_SD, addr); } static inline void flush_icache_line(unsigned long addr) { cache_op(Hit_Invalidate_I, addr); } static inline void flush_dcache_line(unsigned long addr) { cache_op(Hit_Writeback_Inv_D, addr); } static inline void invalidate_dcache_line(unsigned long addr) { cache_op(Hit_Invalidate_D, addr); } static inline void invalidate_scache_line(unsigned long addr) { cache_op(Hit_Invalidate_SD, addr); } static inline void flush_scache_line(unsigned long addr) { cache_op(Hit_Writeback_Inv_SD, addr); } /* * The next two are for badland addresses like signal trampolines. */ static inline void protected_flush_icache_line(unsigned long addr) { __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: cache %0, (%1) \n" "2: .set pop \n" " .section __ex_table,\"a\" \n" " "STR(PTR)" 1b, 2b \n" " .previous" : : "i" (Hit_Invalidate_I), "r" (addr)); } /* * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style * caches. We're talking about one cacheline unnecessarily getting invalidated * here so the penalty isn't overly hard. */ static inline void protected_writeback_dcache_line(unsigned long addr) { __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: cache %0, (%1) \n" "2: .set pop \n" " .section __ex_table,\"a\" \n" " "STR(PTR)" 1b, 2b \n" " .previous" : : "i" (Hit_Writeback_Inv_D), "r" (addr)); } static inline void protected_writeback_scache_line(unsigned long addr) { __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: cache %0, (%1) \n" "2: .set pop \n" " .section __ex_table,\"a\" \n" " "STR(PTR)" 1b, 2b \n" " .previous" : : "i" (Hit_Writeback_Inv_SD), "r" (addr)); } /* * This one is RM7000-specific */ static inline void invalidate_tcache_page(unsigned long addr) { cache_op(Page_Invalidate_T, addr); } #define cache16_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); static inline void blast_dcache16(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } static inline void blast_dcache16_page(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; do { cache16_unroll32(start,Hit_Writeback_Inv_D); start += 0x200; } while (start < end); } static inline void blast_dcache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } static inline void blast_icache16(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_icache16_page(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; do { cache16_unroll32(start,Hit_Invalidate_I); start += 0x200; } while (start < end); } static inline void blast_icache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_scache16(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } static inline void blast_scache16_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; do { cache16_unroll32(start,Hit_Writeback_Inv_SD); start += 0x200; } while (start < end); } static inline void blast_scache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \ " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \ " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \ " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \ " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \ " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \ " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); static inline void blast_dcache32(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } static inline void blast_dcache32_page(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; do { cache32_unroll32(start,Hit_Writeback_Inv_D); start += 0x400; } while (start < end); } static inline void blast_dcache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } static inline void blast_icache32(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_icache32_page(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; do { cache32_unroll32(start,Hit_Invalidate_I); start += 0x400; } while (start < end); } static inline void blast_icache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_scache32(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } static inline void blast_scache32_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; do { cache32_unroll32(start,Hit_Writeback_Inv_SD); start += 0x400; } while (start < end); } static inline void blast_scache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \ " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \ " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \ " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \ " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \ " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \ " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \ " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \ " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); static inline void blast_icache64(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_icache64_page(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; do { cache64_unroll32(start,Hit_Invalidate_I); start += 0x800; } while (start < end); } static inline void blast_icache64_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << current_cpu_data.icache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } static inline void blast_scache64(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } static inline void blast_scache64_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; do { cache64_unroll32(start,Hit_Writeback_Inv_SD); start += 0x800; } while (start < end); } static inline void blast_scache64_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \ " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \ " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \ " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \ " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \ " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \ " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \ " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \ " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \ " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \ " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); static inline void blast_scache128(void) { unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } static inline void blast_scache128_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; do { cache128_unroll32(start,Hit_Writeback_Inv_SD); start += 0x1000; } while (start < end); } static inline void blast_scache128_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } #endif /* _ASM_R4KCACHE_H */ |