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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 | /* * r4kcache.h: Inline assembly cache operations. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * * $Id: r4kcache.h,v 1.7 1997/12/18 13:00:45 ralf Exp $ * * FIXME: Handle split L2 caches. */ #ifndef _MIPS_R4KCACHE_H #define _MIPS_R4KCACHE_H #include <asm/asm.h> #include <asm/cacheops.h> extern inline void flush_icache_line_indexed(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Index_Invalidate_I)); } extern inline void flush_dcache_line_indexed(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Index_Writeback_Inv_D)); } extern inline void flush_scache_line_indexed(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Index_Writeback_Inv_SD)); } extern inline void flush_icache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Hit_Invalidate_I)); } extern inline void flush_dcache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Hit_Writeback_Inv_D)); } extern inline void invalidate_dcache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Hit_Invalidate_D)); } extern inline void invalidate_scache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Hit_Invalidate_SD)); } extern inline void flush_scache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache %1, (%0)\n\t" ".set mips0\n\t" ".set reorder" : : "r" (addr), "i" (Hit_Writeback_Inv_SD)); } /* * The next two are for badland addresses like signal trampolines. */ extern inline void protected_flush_icache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n" "1:\tcache %1,(%0)\n" "2:\t.set mips0\n\t" ".set reorder\n\t" ".section\t__ex_table,\"a\"\n\t" STR(PTR)"\t1b,2b\n\t" ".previous" : : "r" (addr), "i" (Hit_Invalidate_I)); } extern inline void protected_writeback_dcache_line(unsigned long addr) { __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n" "1:\tcache %1,(%0)\n" "2:\t.set mips0\n\t" ".set reorder\n\t" ".section\t__ex_table,\"a\"\n\t" STR(PTR)"\t1b,2b\n\t" ".previous" : : "r" (addr), "i" (Hit_Writeback_D)); } #define cache16_unroll32(base,op) \ __asm__ __volatile__(" \ .set noreorder; \ .set mips3; \ cache %1, 0x000(%0); cache %1, 0x010(%0); \ cache %1, 0x020(%0); cache %1, 0x030(%0); \ cache %1, 0x040(%0); cache %1, 0x050(%0); \ cache %1, 0x060(%0); cache %1, 0x070(%0); \ cache %1, 0x080(%0); cache %1, 0x090(%0); \ cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \ cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \ cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \ cache %1, 0x100(%0); cache %1, 0x110(%0); \ cache %1, 0x120(%0); cache %1, 0x130(%0); \ cache %1, 0x140(%0); cache %1, 0x150(%0); \ cache %1, 0x160(%0); cache %1, 0x170(%0); \ cache %1, 0x180(%0); cache %1, 0x190(%0); \ cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \ cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \ cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \ .set mips0; \ .set reorder" \ : \ : "r" (base), \ "i" (op)); extern inline void blast_dcache16(void) { unsigned long start = KSEG0; unsigned long end = (start + dcache_size); while(start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); start += 0x200; } } extern inline void blast_dcache16_page(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache16_unroll32(start,Hit_Writeback_Inv_D); start += 0x200; } } extern inline void blast_dcache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); start += 0x200; } } extern inline void blast_icache16(void) { unsigned long start = KSEG0; unsigned long end = (start + icache_size); while(start < end) { cache16_unroll32(start,Index_Invalidate_I); start += 0x200; } } extern inline void blast_icache16_page(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache16_unroll32(start,Hit_Invalidate_I); start += 0x200; } } extern inline void blast_icache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache16_unroll32(start,Index_Invalidate_I); start += 0x200; } } extern inline void blast_scache16(void) { unsigned long start = KSEG0; unsigned long end = KSEG0 + scache_size; while(start < end) { cache16_unroll32(start,Index_Writeback_Inv_SD); start += 0x200; } } extern inline void blast_scache16_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache16_unroll32(start,Hit_Writeback_Inv_SD); start += 0x200; } } extern inline void blast_scache16_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache16_unroll32(start,Index_Writeback_Inv_SD); start += 0x200; } } #define cache32_unroll32(base,op) \ __asm__ __volatile__(" \ .set noreorder; \ .set mips3; \ cache %1, 0x000(%0); cache %1, 0x020(%0); \ cache %1, 0x040(%0); cache %1, 0x060(%0); \ cache %1, 0x080(%0); cache %1, 0x0a0(%0); \ cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \ cache %1, 0x100(%0); cache %1, 0x120(%0); \ cache %1, 0x140(%0); cache %1, 0x160(%0); \ cache %1, 0x180(%0); cache %1, 0x1a0(%0); \ cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \ cache %1, 0x200(%0); cache %1, 0x220(%0); \ cache %1, 0x240(%0); cache %1, 0x260(%0); \ cache %1, 0x280(%0); cache %1, 0x2a0(%0); \ cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \ cache %1, 0x300(%0); cache %1, 0x320(%0); \ cache %1, 0x340(%0); cache %1, 0x360(%0); \ cache %1, 0x380(%0); cache %1, 0x3a0(%0); \ cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \ .set mips0; \ .set reorder" \ : \ : "r" (base), \ "i" (op)); extern inline void blast_dcache32(void) { unsigned long start = KSEG0; unsigned long end = (start + dcache_size); while(start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); start += 0x400; } } /* * Call this function only with interrupts disabled or R4600 V2.0 may blow * up on you. * * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Excl_D will only * operate correctly if the internal data cache refill buffer is empty. These * CACHE instructions should be separated from any potential data cache miss * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) */ extern inline void blast_dcache32_page(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); /* * Sigh ... workaround for R4600 v1.7 bug. Explanation see above. */ *(volatile unsigned long *)KSEG1; __asm__ __volatile__("nop;nop;nop;nop"); while(start < end) { cache32_unroll32(start,Hit_Writeback_Inv_D); start += 0x400; } } extern inline void blast_dcache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); start += 0x400; } } extern inline void blast_icache32(void) { unsigned long start = KSEG0; unsigned long end = (start + icache_size); while(start < end) { cache32_unroll32(start,Index_Invalidate_I); start += 0x400; } } extern inline void blast_icache32_page(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache32_unroll32(start,Hit_Invalidate_I); start += 0x400; } } extern inline void blast_icache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = (start + PAGE_SIZE); while(start < end) { cache32_unroll32(start,Index_Invalidate_I); start += 0x400; } } extern inline void blast_scache32(void) { unsigned long start = KSEG0; unsigned long end = KSEG0 + scache_size; while(start < end) { cache32_unroll32(start,Index_Writeback_Inv_SD); start += 0x400; } } extern inline void blast_scache32_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache32_unroll32(start,Hit_Writeback_Inv_SD); start += 0x400; } } extern inline void blast_scache32_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache32_unroll32(start,Index_Writeback_Inv_SD); start += 0x400; } } #define cache64_unroll32(base,op) \ __asm__ __volatile__(" \ .set noreorder; \ .set mips3; \ cache %1, 0x000(%0); cache %1, 0x040(%0); \ cache %1, 0x080(%0); cache %1, 0x0c0(%0); \ cache %1, 0x100(%0); cache %1, 0x140(%0); \ cache %1, 0x180(%0); cache %1, 0x1c0(%0); \ cache %1, 0x200(%0); cache %1, 0x240(%0); \ cache %1, 0x280(%0); cache %1, 0x2c0(%0); \ cache %1, 0x300(%0); cache %1, 0x340(%0); \ cache %1, 0x380(%0); cache %1, 0x3c0(%0); \ cache %1, 0x400(%0); cache %1, 0x440(%0); \ cache %1, 0x480(%0); cache %1, 0x4c0(%0); \ cache %1, 0x500(%0); cache %1, 0x540(%0); \ cache %1, 0x580(%0); cache %1, 0x5c0(%0); \ cache %1, 0x600(%0); cache %1, 0x640(%0); \ cache %1, 0x680(%0); cache %1, 0x6c0(%0); \ cache %1, 0x700(%0); cache %1, 0x740(%0); \ cache %1, 0x780(%0); cache %1, 0x7c0(%0); \ .set mips0; \ .set reorder" \ : \ : "r" (base), \ "i" (op)); extern inline void blast_scache64(void) { unsigned long start = KSEG0; unsigned long end = KSEG0 + scache_size; while(start < end) { cache64_unroll32(start,Index_Writeback_Inv_SD); start += 0x800; } } extern inline void blast_scache64_page(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache64_unroll32(start,Hit_Writeback_Inv_SD); start += 0x800; } } extern inline void blast_scache64_page_indexed(unsigned long page) { unsigned long start = page; unsigned long end = page + PAGE_SIZE; while(start < end) { cache64_unroll32(start,Index_Writeback_Inv_SD); start += 0x800; } } #define cache128_unroll32(base,op) \ __asm__ __volatile__(" \ .set noreorder; \ .set mips3; \ cache %1, 0x000(%0); cache %1, 0x080(%0); \ cache %1, 0x100(%0); cache %1, 0x180(%0); \ cache %1, 0x200(%0); cache %1, 0x280(%0); \ cache %1, 0x300(%0); cache %1, 0x380(%0); \ cache %1, 0x400(%0); cache %1, 0x480(%0); \ cache %1, 0x500(%0); cache %1, 0x580(%0); \ cache %1, 0x600(%0); cache %1, 0x680(%0); \ cache %1, 0x700(%0); cache %1, 0x780(%0); \ cache %1, 0x800(%0); cache %1, 0x880(%0); \ cache %1, 0x900(%0); cache %1, 0x980(%0); \ cache %1, 0xa00(%0); cache %1, 0xa80(%0); \ cache %1, 0xb00(%0); cache %1, 0xb80(%0); \ cache %1, 0xc00(%0); cache %1, 0xc80(%0); \ cache %1, 0xd00(%0); cache %1, 0xd80(%0); \ cache %1, 0xe00(%0); cache %1, 0xe80(%0); \ cache %1, 0xf00(%0); cache %1, 0xf80(%0); \ .set mips0; \ .set reorder" \ : \ : "r" (base), \ "i" (op)); extern inline void blast_scache128(void) { unsigned long start = KSEG0; unsigned long end = KSEG0 + scache_size; while(start < end) { cache128_unroll32(start,Index_Writeback_Inv_SD); start += 0x1000; } } extern inline void blast_scache128_page(unsigned long page) { cache128_unroll32(page,Hit_Writeback_Inv_SD); } extern inline void blast_scache128_page_indexed(unsigned long page) { cache128_unroll32(page,Index_Writeback_Inv_SD); } #endif /* !(_MIPS_R4KCACHE_H) */ |