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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 | [ { "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", "SampleAfterValue": "100003", "UMask": "0x2" }, { "BriefDescription": "Loads with latency value being above 128.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", "PEBS": "2", "SampleAfterValue": "1009", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 16.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", "PEBS": "2", "SampleAfterValue": "20011", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 256.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", "PEBS": "2", "SampleAfterValue": "503", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 32.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", "PEBS": "2", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 4 .", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", "PEBS": "2", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 512.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", "PEBS": "2", "SampleAfterValue": "101", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 64.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", "PEBS": "2", "SampleAfterValue": "2003", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 8.", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", "PEBS": "2", "SampleAfterValue": "50021", "UMask": "0x1" }, { "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400244", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400091", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400240", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400090", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400120", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3004003f7", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400122", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80408fff", "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts LLC replacements.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x6004001b3", "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x17004001b3", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400004", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400001", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80400004", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400002", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80400010", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80400040", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400040", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400010", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400020", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400200", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400080", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x300400100", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80400080", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1f80400200", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", "EventCode": "0xBE", "EventName": "PAGE_WALKS.LLC_MISS", "SampleAfterValue": "100003", "UMask": "0x1" } ] |