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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 | /* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_atombios.h" #include "hdp_v7_0.h" #include "hdp/hdp_7_0_0_offset.h" #include "hdp/hdp_7_0_0_sh_mask.h" #include <uapi/linux/kfd_ioctl.h> static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { if (!ring || !ring->funcs->emit_wreg) WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); else amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); } static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, bool enable) { uint32_t hdp_clk_cntl, hdp_clk_cntl1; uint32_t hdp_mem_pwr_cntl; if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | AMD_CG_SUPPORT_HDP_SD))) return; hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); /* Before doing clock/power mode switch, * forced on IPH & RC clock */ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, RC_MEM_CLK_SOFT_OVERRIDE, 1); WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); /* disable clock and power gating before any changing */ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_CTRL_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_LS_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_DS_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_SD_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_CTRL_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_LS_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_DS_EN, 0); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_SD_EN, 0); WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); /* Already disabled above. The actions below are for "enabled" only */ if (enable) { /* only one clock gating mode (LS/DS/SD) can be enabled */ if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_SD_EN, 1); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_SD_EN, 1); } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_LS_EN, 1); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_LS_EN, 1); } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_DS_EN, 1); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_DS_EN, 1); } /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to * be set for SRAM LS/DS/SD */ if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | AMD_CG_SUPPORT_HDP_SD)) { hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, ATOMIC_MEM_POWER_CTRL_EN, 1); hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, RC_MEM_POWER_CTRL_EN, 1); WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); } } /* disable IPH & RC clock override after clock/power mode changing */ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, RC_MEM_CLK_SOFT_OVERRIDE, 0); WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); } static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { uint32_t tmp; /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) *flags |= AMD_CG_SUPPORT_HDP_LS; else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) *flags |= AMD_CG_SUPPORT_HDP_DS; else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) *flags |= AMD_CG_SUPPORT_HDP_SD; } const struct amdgpu_hdp_funcs hdp_v7_0_funcs = { .flush_hdp = hdp_v7_0_flush_hdp, .update_clock_gating = hdp_v7_0_update_clock_gating, .get_clock_gating_state = hdp_v7_0_get_clockgating_state, }; |