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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 | // SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals * * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { sms: system-controller@44083000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; mboxes = <&secure_proxy_main 11>, <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x00 0x1000>; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; wkup_conf: bus@43000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x43000000 0x20000>; chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; }; secure_proxy_sa3: mailbox@43600000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and * firmware on non-MPU processors */ status = "disabled"; }; mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; ranges = <0x00 0x00 0x41c00000 0x100000>; #address-cells = <1>; #size-cells = <1>; }; wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x02C>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; wkup_pmx2: pinctrl@4301c068 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0x120>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; wkup_pmx3: pinctrl@4301c190 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { compatible = "pinctrl-single"; reg = <0x00 0x40f04200 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; /* Non-MPU Firmware usage */ status = "reserved"; }; /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { compatible = "pinctrl-single"; reg = <0x00 0x40f04280 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; /* Non-MPU Firmware usage */ status = "reserved"; }; wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; reg = <0x00 0x42200000 0x00 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <125>; ti,interrupt-ranges = <16 960 16>; }; mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x40f00000 0x0 0x20000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; #phy-cells = <1>; }; }; mcu_timer0: timer@40400000 { compatible = "ti,am654-timer"; reg = <0x00 0x40400000 0x00 0x400>; interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 35 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer1: timer@40410000 { compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 83 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 83 1>; assigned-clock-parents = <&k3_clks 83 2>; power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer2: timer@40420000 { compatible = "ti,am654-timer"; reg = <0x00 0x40420000 0x00 0x400>; interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 84 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 84 1>; assigned-clock-parents = <&k3_clks 84 2>; power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer3: timer@40430000 { compatible = "ti,am654-timer"; reg = <0x00 0x40430000 0x00 0x400>; interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 85 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 85 1>; assigned-clock-parents = <&k3_clks 85 2>; power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer4: timer@40440000 { compatible = "ti,am654-timer"; reg = <0x00 0x40440000 0x00 0x400>; interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 86 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 86 1>; assigned-clock-parents = <&k3_clks 86 2>; power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer5: timer@40450000 { compatible = "ti,am654-timer"; reg = <0x00 0x40450000 0x00 0x400>; interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 87 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 87 1>; assigned-clock-parents = <&k3_clks 87 2>; power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer6: timer@40460000 { compatible = "ti,am654-timer"; reg = <0x00 0x40460000 0x00 0x400>; interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 88 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 88 1>; assigned-clock-parents = <&k3_clks 88 2>; power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer7: timer@40470000 { compatible = "ti,am654-timer"; reg = <0x00 0x40470000 0x00 0x400>; interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 89 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 89 1>; assigned-clock-parents = <&k3_clks 89 2>; power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer8: timer@40480000 { compatible = "ti,am654-timer"; reg = <0x00 0x40480000 0x00 0x400>; interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 90 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 90 1>; assigned-clock-parents = <&k3_clks 90 2>; power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer9: timer@40490000 { compatible = "ti,am654-timer"; reg = <0x00 0x40490000 0x00 0x400>; interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 91 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; current-speed = <115200>; clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x200>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; current-speed = <115200>; clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; wkup_gpio0: gpio@42110000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x42110000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&wkup_gpio_intr>; interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <89>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 115 0>; clock-names = "gpio"; status = "disabled"; }; wkup_gpio1: gpio@42100000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x42100000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&wkup_gpio_intr>; interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <89>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 116 0>; clock-names = "gpio"; status = "disabled"; }; wkup_i2c0: i2c@42120000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x42120000 0x00 0x100>; interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcu_i2c0: i2c@40b00000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x40b00000 0x00 0x100>; interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 221 1>; clock-names = "fck"; power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcu_i2c1: i2c@40b10000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x40b10000 0x00 0x100>; interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 222 1>; clock-names = "fck"; power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; mcu_mcan0: can@40528000 { compatible = "bosch,m_can"; reg = <0x00 0x40528000 0x00 0x200>, <0x00 0x40500000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; mcu_mcan1: can@40568000 { compatible = "bosch,m_can"; reg = <0x00 0x40568000 0x00 0x200>, <0x00 0x40540000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; mcu_spi0: spi@40300000 { compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; reg = <0x00 0x040300000 0x00 0x400>; interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 347 0>; status = "disabled"; }; mcu_spi1: spi@40310000 { compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; reg = <0x00 0x040310000 0x00 0x400>; interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 348 0>; status = "disabled"; }; mcu_spi2: spi@40320000 { compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; reg = <0x00 0x040320000 0x00 0x400>; interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 349 0>; status = "disabled"; }; mcu_navss: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; dma-coherent; dma-ranges; ti,sci-dev-id = <267>; mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; ti,sci-dev-id = <272>; msi-parent = <&main_udmass_inta>; }; mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; reg = <0x0 0x285c0000 0x0 0x100>, <0x0 0x2a800000 0x0 0x40000>, <0x0 0x2aa00000 0x0 0x40000>, <0x0 0x284a0000 0x0 0x4000>, <0x0 0x284c0000 0x0 0x4000>, <0x0 0x28400000 0x0 0x2000>; reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <273>; ti,ringacc = <&mcu_ringacc>; ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ <0x0f>; /* TX_HCHAN */ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ <0x0b>; /* RX_HCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; }; secure_proxy_mcu: mailbox@2a480000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and * firmware on non-MPU processors */ status = "disabled"; }; mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; #size-cells = <2>; reg = <0x0 0x46000000 0x0 0x200000>; reg-names = "cpsw_nuss"; ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; dma-coherent; clocks = <&k3_clks 29 28>; clock-names = "fck"; power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; dmas = <&mcu_udmap 0xf000>, <&mcu_udmap 0xf001>, <&mcu_udmap 0xf002>, <&mcu_udmap 0xf003>, <&mcu_udmap 0xf004>, <&mcu_udmap 0xf005>, <&mcu_udmap 0xf006>, <&mcu_udmap 0xf007>, <&mcu_udmap 0x7000>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; cpsw_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; ti,syscon-efuse = <&mcu_conf 0x200>; phys = <&phy_gmii_sel 1>; }; }; davinci_mdio: mdio@f00 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x0 0xf00 0x0 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 29 28>; clock-names = "fck"; bus_freq = <1000000>; }; cpts@3d000 { compatible = "ti,am65-cpts"; reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 29 3>; clock-names = "cpts"; assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; ti,cpts-periodic-outputs = <2>; }; }; tscadc0: tscadc@40200000 { compatible = "ti,am3359-tscadc"; reg = <0x00 0x40200000 0x00 0x1000>; interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 0 0>; assigned-clocks = <&k3_clks 0 2>; assigned-clock-rates = <60000000>; clock-names = "fck"; dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; status = "disabled"; adc { #io-channel-cells = <1>; compatible = "ti,am3359-adc"; }; }; tscadc1: tscadc@40210000 { compatible = "ti,am3359-tscadc"; reg = <0x00 0x40210000 0x00 0x1000>; interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 1 0>; assigned-clocks = <&k3_clks 1 2>; assigned-clock-rates = <60000000>; clock-names = "fck"; dmas = <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names = "fifo0", "fifo1"; status = "disabled"; adc { #io-channel-cells = <1>; compatible = "ti,am3359-adc"; }; }; fss: bus@47000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x00 0x47040000 0x00 0x100>, <0x05 0x00000000 0x01 0x00000000>; interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; clocks = <&k3_clks 109 5>; assigned-clocks = <&k3_clks 109 5>; assigned-clock-parents = <&k3_clks 109 7>; assigned-clock-rates = <166666666>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; /* Needs pinmux */ }; ospi1: spi@47050000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x00 0x47050000 0x00 0x100>, <0x07 0x00000000 0x01 0x00000000>; interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; clocks = <&k3_clks 110 5>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; /* Needs pinmux */ }; }; wkup_vtm0: temperature-sensor@42040000 { compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x0 0x350>, <0x00 0x42050000 0x0 0x350>; power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721s2-r5fss"; ti,cluster-mode = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721s2-r5f"; reg = <0x41000000 0x00010000>, <0x41010000 0x00010000>; reg-names = "atcm", "btcm"; ti,sci = <&sms>; ti,sci-dev-id = <284>; ti,sci-proc-ids = <0x01 0xff>; resets = <&k3_reset 284 1>; firmware-name = "j721s2-mcu-r5f0_0-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; mcu_r5fss0_core1: r5f@41400000 { compatible = "ti,j721s2-r5f"; reg = <0x41400000 0x00010000>, <0x41410000 0x00010000>; reg-names = "atcm", "btcm"; ti,sci = <&sms>; ti,sci-dev-id = <285>; ti,sci-proc-ids = <0x02 0xff>; resets = <&k3_reset 285 1>; firmware-name = "j721s2-mcu-r5f0_1-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; }; mcu_esm: esm@40800000 { compatible = "ti,j721e-esm"; reg = <0x00 0x40800000 0x00 0x1000>; ti,esm-pins = <95>; bootph-pre-ram; }; wkup_esm: esm@42080000 { compatible = "ti,j721e-esm"; reg = <0x00 0x42080000 0x00 0x1000>; ti,esm-pins = <63>; bootph-pre-ram; }; /* * The 2 RTI instances are couple with MCU R5Fs so keeping them * reserved as these will be used by their respective firmware */ mcu_watchdog0: watchdog@40600000 { compatible = "ti,j7-rti-wdt"; reg = <0x00 0x40600000 0x00 0x100>; clocks = <&k3_clks 295 1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 295 1>; assigned-clock-parents = <&k3_clks 295 5>; /* reserved for MCU_R5F0_0 */ status = "reserved"; }; mcu_watchdog1: watchdog@40610000 { compatible = "ti,j7-rti-wdt"; reg = <0x00 0x40610000 0x00 0x100>; clocks = <&k3_clks 296 1>; power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 296 1>; assigned-clock-parents = <&k3_clks 296 5>; /* reserved for MCU_R5F0_1 */ status = "reserved"; }; }; |