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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 | /* * Allwinner H3 SoCs pinctrl driver. * * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin sun8i_h3_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_pwm"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_cir_rx"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ }; static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = { .pins = sun8i_h3_r_pins, .npins = ARRAY_SIZE(sun8i_h3_r_pins), .irq_banks = 1, .pin_base = PL_BASE, .irq_read_needs_mux = true, .disable_strict_mode = true, }; static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) { return sunxi_pinctrl_init(pdev, &sun8i_h3_r_pinctrl_data); } static const struct of_device_id sun8i_h3_r_pinctrl_match[] = { { .compatible = "allwinner,sun8i-h3-r-pinctrl", }, {} }; static struct platform_driver sun8i_h3_r_pinctrl_driver = { .probe = sun8i_h3_r_pinctrl_probe, .driver = { .name = "sun8i-h3-r-pinctrl", .of_match_table = sun8i_h3_r_pinctrl_match, }, }; builtin_platform_driver(sun8i_h3_r_pinctrl_driver); |