// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_PCIE_3_PIPE,
DT_PCIE_4_PIPE,
DT_PCIE_5_PIPE,
DT_PCIE_6A_PIPE,
DT_PCIE_6B_PIPE,
DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
};
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL8_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52030,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52030,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll7",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll8 = {
.offset = 0x8000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52030,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll8",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52030,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL8_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll8.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0xa0180,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0xa0054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x2c180,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x2c054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
.cmd_rcgr = 0x13180,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
.cmd_rcgr = 0x13054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
.cmd_rcgr = 0x5808c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
.cmd_rcgr = 0x58070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
.cmd_rcgr = 0x6b080,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
.cmd_rcgr = 0x2f080,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
.cmd_rcgr = 0x2f064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
.cmd_rcgr = 0x3108c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
.cmd_rcgr = 0x31070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
.cmd_rcgr = 0x8d08c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
.cmd_rcgr = 0x8d070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
.cmd_rcgr = 0xa400c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_xo_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x42010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x42148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x42288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x423c8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x42500,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x42638,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x42770,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x428a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183c8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x18500,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18638,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18770,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x188a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e3c8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e500,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e638,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x1e770,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
.name = "gcc_qupv3_wrap2_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
.cmd_rcgr = 0x1e8a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x14018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x16018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77030,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77080,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77098,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb20_master_clk_src = {
.cmd_rcgr = 0x2902c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb20_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x29158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
.cmd_rcgr = 0x1702c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
.cmd_rcgr = 0x17158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x3902c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x39044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0xa102c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0xa1044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
.cmd_rcgr = 0xa202c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
.cmd_rcgr = 0xa2044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
.cmd_rcgr = 0x172a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x39074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0xa1074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
.cmd_rcgr = 0xa2074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_tert_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
.cmd_rcgr = 0x9f024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_master_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
.cmd_rcgr = 0x9f0e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
.cmd_rcgr = 0x9f08c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_sb_if_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
.cmd_rcgr = 0x9f070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_tmu_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
.cmd_rcgr = 0x2b024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_master_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
.cmd_rcgr = 0x2b0e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
.cmd_rcgr = 0x2b08c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sb_if_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
.cmd_rcgr = 0x2b070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_tmu_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
.cmd_rcgr = 0x11024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_master_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
.cmd_rcgr = 0x110e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
.cmd_rcgr = 0x1108c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_sb_if_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
.cmd_rcgr = 0x11070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_tmu_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = {
.reg = 0x58088,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_3_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = {
.reg = 0x5806c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_3_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
.reg = 0x6b07c,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_4_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_4_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
.reg = 0x6b060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_4_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
.reg = 0x2f07c,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_5_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_5_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
.reg = 0x2f060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_5_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = {
.reg = 0x31088,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_6a_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_6A_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = {
.reg = 0x3106c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6a_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = {
.reg = 0x8d088,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_6b_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_6B_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = {
.reg = 0x8d06c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6b_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = {
.reg = 0x42284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = {
.reg = 0x423c4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s3_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = {
.reg = 0x18284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = {
.reg = 0x183c4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s3_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = {
.reg = 0x1e284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = {
.reg = 0x1e3c4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s3_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
.reg = 0x29284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
.reg = 0x17284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x3905c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0xa105c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
.reg = 0xa205c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = {
.halt_reg = 0x2d17c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d17c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2d17c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_usb_north_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = {
.halt_reg = 0x2d174,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d174,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2d174,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_usb_south_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770e4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770e4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
.halt_reg = 0x2928c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2928c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2928c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb2_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
.halt_reg = 0x173d0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x173d0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x173d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x39090,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x39090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x39090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0xa1090,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa1090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa1090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
.halt_reg = 0xa2090,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa2090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_tert_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_tert_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
.halt_reg = 0x9f118,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9f118,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9f118,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb4_0_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
.halt_reg = 0x2b118,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b118,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2b118,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb4_1_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_1_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
.halt_reg = 0x11118,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x11118,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x11118,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb4_2_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_2_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
.halt_reg = 0x2d034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2d034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb_noc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_av1e_ahb_clk = {
.halt_reg = 0x4a004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_av1e_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_av1e_axi_clk = {
.halt_reg = 0x4a008,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x4a008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4a008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_av1e_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_av1e_xo_clk = {
.halt_reg = 0x4a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4a014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_av1e_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x2601c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2601c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2601c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
.halt_reg = 0x10028,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = {
.halt_reg = 0x1002c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1002c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
.halt_reg = 0x10030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
.halt_reg = 0x29288,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x29288,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x29288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb2_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
.halt_reg = 0x173cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x173cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x173cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x3908c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3908c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3908c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0xa108c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa108c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa108c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
.halt_reg = 0xa208c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa208c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa208c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_tert_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_tert_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
.halt_reg = 0x2d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb_anoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = {
.halt_reg = 0x2d028,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb_anoc_north_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
.halt_reg = 0x2d02c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d02c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
.halt_reg = 0x2c2b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie1_tunnel_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = {
.halt_reg = 0x132b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie2_tunnel_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = {
.halt_reg = 0x10014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie_north_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie_south_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie_tunnel_clk = {
.halt_reg = 0xa02b4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa02b4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie_tunnel_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x7115c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x7115c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7115c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x27018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_cph_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_div_cph_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_rchng_clk = {
.halt_reg = 0xa0050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_rchng_clk = {
.halt_reg = 0x2c050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_phy_rchng_clk = {
.halt_reg = 0x13050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0xa0038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0xa0034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa0034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0xa0028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa0028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0xa0044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0xa001c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa001c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0xa0018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x2c038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x2c034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2c034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x2c028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2c028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x2c044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x2c01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2c01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x2c018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_aux_clk = {
.halt_reg = 0x13038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.halt_reg = 0x13034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x13034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.halt_reg = 0x13028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x13028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x13044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.halt_reg = 0x1301c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1301c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
.halt_reg = 0x13018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_aux_clk = {
.halt_reg = 0x58038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
.halt_reg = 0x58034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x58034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
.halt_reg = 0x58028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x58028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_phy_aux_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_phy_aux_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_phy_rchng_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_3_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_pipe_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_pipediv2_clk = {
.halt_reg = 0x58060,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_3_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_slv_axi_clk = {
.halt_reg = 0x5801c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5801c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
.halt_reg = 0x58018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_aux_clk = {
.halt_reg = 0x6b038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_4_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
.halt_reg = 0x6b034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
.halt_reg = 0x6b028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
.halt_reg = 0x6b050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_pipe_clk = {
.halt_reg = 0x6b044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_pipediv2_clk = {
.halt_reg = 0x6b054,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_slv_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_aux_clk = {
.halt_reg = 0x2f038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_5_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
.halt_reg = 0x2f034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2f034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
.halt_reg = 0x2f028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2f028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
.halt_reg = 0x2f050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_pipe_clk = {
.halt_reg = 0x2f044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_pipediv2_clk = {
.halt_reg = 0x2f054,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_5_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_slv_axi_clk = {
.halt_reg = 0x2f01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2f01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
.halt_reg = 0x2f018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_5_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_aux_clk = {
.halt_reg = 0x31038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6a_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = {
.halt_reg = 0x31034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x31034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_mstr_axi_clk = {
.halt_reg = 0x31028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x31028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_phy_aux_clk = {
.halt_reg = 0x31044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_phy_aux_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {
.halt_reg = 0x3105c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6a_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_pipe_clk = {
.halt_reg = 0x31050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
.halt_reg = 0x31060,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6a_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_slv_axi_clk = {
.halt_reg = 0x3101c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3101c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = {
.halt_reg = 0x31018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6a_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_aux_clk = {
.halt_reg = 0x8d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6b_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = {
.halt_reg = 0x8d034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_mstr_axi_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_phy_aux_clk = {
.halt_reg = 0x8d044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_phy_aux_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {
.halt_reg = 0x8d05c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6b_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_pipe_clk = {
.halt_reg = 0x8d050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
.halt_reg = 0x8d060,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_6b_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_slv_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_6b_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rscc_ahb_clk = {
.halt_reg = 0xa4008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa4008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rscc_xo_clk = {
.halt_reg = 0xa4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_rscc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_av1e_ahb_clk = {
.halt_reg = 0x4a018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4a018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4a018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_av1e_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_ahb_clk = {
.halt_reg = 0x71008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_gpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
.halt_reg = 0x32014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_cv_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x32008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
.halt_reg = 0x32010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_v_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x3200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x23018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
.halt_reg = 0x42280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_qspi_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
.halt_reg = 0x423c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_qspi_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x42004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x4213c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x42274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x423b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x424f4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x4262c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x42764,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x4289c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x23168,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23158,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
.halt_reg = 0x18280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_qspi_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
.halt_reg = 0x183c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_qspi_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x1813c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x183b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184f4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x1862c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18764,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x1889c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x232b8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x232a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
.halt_reg = 0x1e280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_qspi_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
.halt_reg = 0x1e3c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_qspi_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e13c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e3b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e4f4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e62c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x1e764,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
.halt_reg = 0x1e89c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x23150,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23150,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x23154,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x232a0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x232a0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x232a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x232a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb_axi_clk = {
.halt_reg = 0x2d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2d014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_usb_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77074,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x770b0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770b0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7702c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x77028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x29018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x29028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_sleep_clk = {
.halt_reg = 0x29024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_master_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_sleep_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x39018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x39028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x39024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0xa1018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa1018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0xa1028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa1028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0xa1024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa1024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_tert_master_clk = {
.halt_reg = 0xa2018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_tert_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
.halt_reg = 0xa2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_tert_sleep_clk = {
.halt_reg = 0xa2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_tert_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
.halt_reg = 0x17288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
.halt_reg = 0x1728c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1728c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
.halt_reg = 0x17290,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17290,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
.halt_reg = 0x17298,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17298,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x39060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x39064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x3906c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x39068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x39068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x39068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0xa1060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa1060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0xa1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa1064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0xa106c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0xa1068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa1068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa1068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
.halt_reg = 0xa2060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_tert_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
.halt_reg = 0xa2064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_tert_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
.reg = 0xa206c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_tert_phy_pipe_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
.halt_reg = 0xa2068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa2068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_tert_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
.halt_reg = 0x9f0a8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9f0a8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9f0a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_dp0_clk = {
.halt_reg = 0x9f060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_dp0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_dp1_clk = {
.halt_reg = 0x9f108,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_dp1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_master_clk = {
.halt_reg = 0x9f018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x9f0d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f0d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
.halt_reg = 0x9f048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_pcie_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
.halt_reg = 0x9f0b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f0b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_rx0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
.halt_reg = 0x9f0c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f0c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_rx1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
.halt_reg = 0x9f0a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9f0a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9f0a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_phy_usb_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_sb_if_clk = {
.halt_reg = 0x9f044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_sb_if_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_0_sb_if_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_sys_clk = {
.halt_reg = 0x9f054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_sys_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_0_tmu_clk = {
.halt_reg = 0x9f088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9f088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9f088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_0_tmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_0_tmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
.halt_reg = 0x2b0a8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b0a8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2b0a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_dp0_clk = {
.halt_reg = 0x2b060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_dp0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_dp1_clk = {
.halt_reg = 0x2b108,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_dp1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_master_clk = {
.halt_reg = 0x2b018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_1_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x2b0d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b0d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
.halt_reg = 0x2b048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
.halt_reg = 0x2b0b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b0b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
.halt_reg = 0x2b0c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b0c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
.halt_reg = 0x2b0a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b0a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2b0a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_usb_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_sb_if_clk = {
.halt_reg = 0x2b044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sb_if_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_1_sb_if_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_sys_clk = {
.halt_reg = 0x2b054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sys_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_tmu_clk = {
.halt_reg = 0x2b088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2b088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_tmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_1_tmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
.halt_reg = 0x110a8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x110a8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x110a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_dp0_clk = {
.halt_reg = 0x11060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_dp0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_dp1_clk = {
.halt_reg = 0x11108,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_dp1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_master_clk = {
.halt_reg = 0x11018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_2_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x110d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x110d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
.halt_reg = 0x11048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_pcie_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
.halt_reg = 0x110b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x110b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_rx0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
.halt_reg = 0x110c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x110c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_rx1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
.halt_reg = 0x110a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x110a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x110a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_phy_usb_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_sb_if_clk = {
.halt_reg = 0x11044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_sb_if_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_2_sb_if_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_sys_clk = {
.halt_reg = 0x11054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_sys_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_2_tmu_clk = {
.halt_reg = 0x11088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x11088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x11088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_2_tmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb4_2_tmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x32018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x32024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gcc_pcie_0_tunnel_gdsc = {
.gdscr = 0xa0004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_0_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_1_tunnel_gdsc = {
.gdscr = 0x2c004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_1_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_2_tunnel_gdsc = {
.gdscr = 0x13004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_2_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_3_gdsc = {
.gdscr = 0x58004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_3_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_3_phy_gdsc = {
.gdscr = 0x3e000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_3_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_4_gdsc = {
.gdscr = 0x6b004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_4_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_4_phy_gdsc = {
.gdscr = 0x6c000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_4_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_5_gdsc = {
.gdscr = 0x2f004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_5_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_5_phy_gdsc = {
.gdscr = 0x30000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_5_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_6_phy_gdsc = {
.gdscr = 0x8e000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_6_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_6a_gdsc = {
.gdscr = 0x31004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_6a_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_6b_gdsc = {
.gdscr = 0x8d004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_6b_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_ufs_mem_phy_gdsc = {
.gdscr = 0x9e000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_ufs_mem_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_ufs_phy_gdsc = {
.gdscr = 0x77004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb20_prim_gdsc = {
.gdscr = 0x29004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb20_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_mp_gdsc = {
.gdscr = 0x17004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_mp_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_prim_gdsc = {
.gdscr = 0x39004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_sec_gdsc = {
.gdscr = 0xa1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_sec_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_tert_gdsc = {
.gdscr = 0xa2004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_tert_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
.gdscr = 0x1900c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb3_mp_ss0_phy_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
.gdscr = 0x5400c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb3_mp_ss1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb4_0_gdsc = {
.gdscr = 0x9f004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb4_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb4_1_gdsc = {
.gdscr = 0x2b004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb4_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb4_2_gdsc = {
.gdscr = 0x11004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb4_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb_0_phy_gdsc = {
.gdscr = 0x50024,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb_0_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb_1_phy_gdsc = {
.gdscr = 0x2a024,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb_1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb_2_phy_gdsc = {
.gdscr = 0xa3024,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb_2_phy_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gcc_x1e80100_clocks[] = {
[GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr,
[GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
[GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
[GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
[GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
[GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
[GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr,
[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
[GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr,
[GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr,
[GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr,
[GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL8] = &gcc_gpll8.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
[GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
[GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr,
[GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr,
[GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr,
[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
[GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr,
[GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr,
[GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr,
[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
[GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
[GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
[GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
[GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
[GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
[GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
[GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
[GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
[GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
[GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
[GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr,
[GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
[GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
[GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr,
[GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr,
[GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr,
[GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr,
[GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr,
[GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr,
[GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr,
[GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr,
[GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr,
[GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr,
[GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr,
[GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr,
[GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr,
[GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr,
[GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr,
[GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr,
[GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr,
[GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr,
[GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr,
[GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr,
[GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr,
[GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr,
[GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr,
[GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr,
[GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr,
[GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr,
[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
[GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
[GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
[GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
[GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
[GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
[GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
[GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
[GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
[GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
[GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
[GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
[GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
[GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
[GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
[GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
[GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
[GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
[GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
[GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
[GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static struct gdsc *gcc_x1e80100_gdscs[] = {
[GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
[GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
[GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
[GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc,
[GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc,
[GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
[GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
[GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
[GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
[GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
[GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc,
[GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc,
[GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
[GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
[GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
[GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
[GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
[GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
[GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
[GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
[GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
[GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
[GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
[GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
};
static const struct qcom_reset_map gcc_x1e80100_resets[] = {
[GCC_AV1E_BCR] = { 0x4a000 },
[GCC_CAMERA_BCR] = { 0x26000 },
[GCC_DISPLAY_BCR] = { 0x27000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
[GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
[GCC_PCIE_2_PHY_BCR] = { 0xa501c },
[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
[GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
[GCC_PCIE_3_BCR] = { 0x58000 },
[GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
[GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
[GCC_PCIE_3_PHY_BCR] = { 0xab01c },
[GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
[GCC_PCIE_4_BCR] = { 0x6b000 },
[GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
[GCC_PCIE_4_PHY_BCR] = { 0xb301c },
[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
[GCC_PCIE_5_BCR] = { 0x2f000 },
[GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
[GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
[GCC_PCIE_6A_BCR] = { 0x31000 },
[GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
[GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
[GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
[GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
[GCC_PCIE_6B_BCR] = { 0x8d000 },
[GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
[GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
[GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
[GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PCIE_RSCC_BCR] = { 0xa4000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
[GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB20_PRIM_BCR] = { 0x29000 },
[GCC_USB30_MP_BCR] = { 0x17000 },
[GCC_USB30_PRIM_BCR] = { 0x39000 },
[GCC_USB30_SEC_BCR] = { 0xa1000 },
[GCC_USB30_TERT_BCR] = { 0xa2000 },
[GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
[GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
[GCC_USB4_0_BCR] = { 0x9f000 },
[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
[GCC_USB4_1_BCR] = { 0x2b000 },
[GCC_USB4_2_BCR] = { 0x11000 },
[GCC_USB_0_PHY_BCR] = { 0x50020 },
[GCC_USB_1_PHY_BCR] = { 0x2a020 },
[GCC_USB_2_PHY_BCR] = { 0xa3020 },
[GCC_VIDEO_BCR] = { 0x32000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
};
static const struct regmap_config gcc_x1e80100_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f41f0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_x1e80100_desc = {
.config = &gcc_x1e80100_regmap_config,
.clks = gcc_x1e80100_clocks,
.num_clks = ARRAY_SIZE(gcc_x1e80100_clocks),
.resets = gcc_x1e80100_resets,
.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
.gdscs = gcc_x1e80100_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
};
static const struct of_device_id gcc_x1e80100_match_table[] = {
{ .compatible = "qcom,x1e80100-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table);
static int gcc_x1e80100_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52224, 0x0);
return qcom_cc_really_probe(pdev, &gcc_x1e80100_desc, regmap);
}
static struct platform_driver gcc_x1e80100_driver = {
.probe = gcc_x1e80100_probe,
.driver = {
.name = "gcc-x1e80100",
.of_match_table = gcc_x1e80100_match_table,
},
};
static int __init gcc_x1e80100_init(void)
{
return platform_driver_register(&gcc_x1e80100_driver);
}
subsys_initcall(gcc_x1e80100_init);
static void __exit gcc_x1e80100_exit(void)
{
platform_driver_unregister(&gcc_x1e80100_driver);
}
module_exit(gcc_x1e80100_exit);
MODULE_DESCRIPTION("QTI GCC X1E80100 Driver");
MODULE_LICENSE("GPL");
