Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2016 NXP Semiconductors. * Author: Fabio Estevam <fabio.estevam@nxp.com> */ /dts-v1/; #include <dt-bindings/input/input.h> #include "imx7s.dtsi" / { model = "Element14 Warp i.MX7 Board"; compatible = "element14,imx7s-warp", "fsl,imx7s"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; }; gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&pinctrl_gpio>; autorepeat; back { label = "Back"; gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; linux,code = <KEY_BACK>; wakeup-source; }; }; reg_brcm: regulator-brcm { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_brcm_reg>; regulator-name = "brcm_reg"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <200000>; }; reg_bt: regulator-bt { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt_reg>; enable-active-high; gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; regulator-name = "bt_reg"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_peri_3p15v: regulator-peri-3p15v { compatible = "regulator-fixed"; regulator-name = "peri_3p15v_reg"; regulator-min-microvolt = <3150000>; regulator-max-microvolt = <3150000>; regulator-always-on; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,cpu { sound-dai = <&sai1>; }; dailink_master: simple-audio-card,codec { sound-dai = <&codec>; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; &clks { assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <884736000>; }; &csi { status = "okay"; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; regulators { sw1a_reg: sw1a { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1475000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; /* use sw1c_reg to align with pfuze100/pfuze200 */ sw1c_reg: sw1b { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1475000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; sw2_reg: sw2 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1850000>; regulator-boot-on; regulator-always-on; }; sw3a_reg: sw3 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1650000>; regulator-boot-on; regulator-always-on; }; swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; regulator-boot-on; regulator-always-on; }; snvs_reg: vsnvs { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; regulator-boot-on; regulator-always-on; }; vref_reg: vrefddr { regulator-boot-on; regulator-always-on; }; vgen1_reg: vldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen2_reg: vldo2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; }; vgen3_reg: vccsd { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen4_reg: v33 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen5_reg: vldo3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen6_reg: vldo4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; ov2680: camera@36 { compatible = "ovti,ov2680"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov2680>; reg = <0x36>; clocks = <&osc>; clock-names = "xvclk"; reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; DOVDD-supply = <&sw2_reg>; DVDD-supply = <&sw2_reg>; AVDD-supply = <®_peri_3p15v>; port { ov2680_to_mipi: endpoint { remote-endpoint = <&mipi_from_sensor>; clock-lanes = <0>; data-lanes = <1>; }; }; }; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; }; &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; codec: sgtl5000@a { #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <&vgen4_reg>; VDDIO-supply = <&vgen4_reg>; VDDD-supply = <&vgen2_reg>; }; mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; }; }; &mipi_csi { clock-frequency = <166000000>; status = "okay"; ports { port@0 { reg = <0>; mipi_from_sensor: endpoint { remote-endpoint = <&ov2680_to_mipi>; data-lanes = <1>; }; }; }; }; &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, <&clks IMX7D_SAI1_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <36864000>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; uart-has-rtscts; status = "okay"; }; &uart6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; fsl,dte-mode; status = "okay"; }; &usbotg1 { dr_mode = "peripheral"; status = "okay"; }; &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; bus-width = <4>; keep-power-in-suspend; no-1-8-v; non-removable; vmmc-supply = <®_brcm>; status = "okay"; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; no-1-8-v; fsl,tuning-step = <2>; non-removable; status = "okay"; }; &video_mux { status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ >; }; pinctrl_bt_reg: btreggrp { fsl,pins = < MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ >; }; pinctrl_gpio: gpiogrp { fsl,pins = < MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f >; }; pinctrl_ov2680: ov2660grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 >; }; pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 >; }; pinctrl_sai1_mclk: sai1mclkgrp { fsl,pins = < MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 >; }; pinctrl_uart6: uart6grp { fsl,pins = < MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 >; }; pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x1a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a >; }; pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b MX7D_PAD_SD3_CLK__SD3_CLK 0x1b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b >; }; }; &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; }; |