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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 | /* * Copyright 2018 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #define gv100_dmaobj(p) container_of((p), struct gv100_dmaobj, base) #include "user.h" #include <core/client.h> #include <core/gpuobj.h> #include <subdev/fb.h> #include <nvif/cl0002.h> #include <nvif/unpack.h> struct gv100_dmaobj { struct nvkm_dmaobj base; u32 flags0; }; static int gv100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) { struct gv100_dmaobj *dmaobj = gv100_dmaobj(base); struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; u64 start = dmaobj->base.start >> 8; u64 limit = dmaobj->base.limit >> 8; int ret; ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start)); nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start)); nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit)); nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit)); nvkm_done(*pgpuobj); } return ret; } static const struct nvkm_dmaobj_func gv100_dmaobj_func = { .bind = gv100_dmaobj_bind, }; int gv100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_dmaobj **pdmaobj) { union { struct gf119_dma_v0 v0; } *args; struct nvkm_object *parent = oclass->parent; struct gv100_dmaobj *dmaobj; u32 kind, page; int ret; if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL))) return -ENOMEM; *pdmaobj = &dmaobj->base; ret = nvkm_dmaobj_ctor(&gv100_dmaobj_func, dma, oclass, &data, &size, &dmaobj->base); if (ret) return ret; ret = -ENOSYS; args = data; nvif_ioctl(parent, "create gv100 dma size %d\n", size); if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create gv100 dma vers %d page %d kind %02x\n", args->v0.version, args->v0.page, args->v0.kind); kind = args->v0.kind != 0; page = args->v0.page != 0; } else if (size == 0) { kind = 0; page = GF119_DMA_V0_PAGE_SP; } else return ret; if (kind) dmaobj->flags0 |= 0x00100000; if (page) dmaobj->flags0 |= 0x00000040; dmaobj->flags0 |= 0x00000004; /* rw */ switch (dmaobj->base.target) { case NV_MEM_TARGET_VRAM : dmaobj->flags0 |= 0x00000001; break; case NV_MEM_TARGET_PCI : dmaobj->flags0 |= 0x00000002; break; case NV_MEM_TARGET_PCI_NOSNOOP: dmaobj->flags0 |= 0x00000003; break; default: return -EINVAL; } return 0; } |