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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 | /* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _ASM_X86_XOR_32_H #define _ASM_X86_XOR_32_H /* * Optimized RAID-5 checksumming functions for MMX. */ /* * High-speed RAID5 checksumming functions utilizing MMX instructions. * Copyright (C) 1998 Ingo Molnar. */ #define LD(x, y) " movq 8*("#x")(%1), %%mm"#y" ;\n" #define ST(x, y) " movq %%mm"#y", 8*("#x")(%1) ;\n" #define XO1(x, y) " pxor 8*("#x")(%2), %%mm"#y" ;\n" #define XO2(x, y) " pxor 8*("#x")(%3), %%mm"#y" ;\n" #define XO3(x, y) " pxor 8*("#x")(%4), %%mm"#y" ;\n" #define XO4(x, y) " pxor 8*("#x")(%5), %%mm"#y" ;\n" #include <asm/fpu/api.h> static void xor_pII_mmx_2(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ ST(i, 0) \ XO1(i+1, 1) \ ST(i+1, 1) \ XO1(i + 2, 2) \ ST(i + 2, 2) \ XO1(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_3(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ ST(i, 0) \ XO2(i + 1, 1) \ ST(i + 1, 1) \ XO2(i + 2, 2) \ ST(i + 2, 2) \ XO2(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_4(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ XO2(i + 1, 1) \ XO2(i + 2, 2) \ XO2(i + 3, 3) \ XO3(i, 0) \ ST(i, 0) \ XO3(i + 1, 1) \ ST(i + 1, 1) \ XO3(i + 2, 2) \ ST(i + 2, 2) \ XO3(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " addl $128, %4 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_5(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4, const unsigned long * __restrict p5) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); /* Make sure GCC forgets anything it knows about p4 or p5, such that it won't pass to the asm volatile below a register that is shared with any other variable. That's because we modify p4 and p5 there, but we can't mark them as read/write, otherwise we'd overflow the 10-asm-operands limit of GCC < 3.1. */ asm("" : "+r" (p4), "+r" (p5)); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ XO2(i + 1, 1) \ XO2(i + 2, 2) \ XO2(i + 3, 3) \ XO3(i, 0) \ XO3(i + 1, 1) \ XO3(i + 2, 2) \ XO3(i + 3, 3) \ XO4(i, 0) \ ST(i, 0) \ XO4(i + 1, 1) \ ST(i + 1, 1) \ XO4(i + 2, 2) \ ST(i + 2, 2) \ XO4(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " addl $128, %4 ;\n" " addl $128, %5 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : "r" (p4), "r" (p5) : "memory"); /* p4 and p5 were modified, and now the variables are dead. Clobber them just to be sure nobody does something stupid like assuming they have some legal value. */ asm("" : "=r" (p4), "=r" (p5)); kernel_fpu_end(); } #undef LD #undef XO1 #undef XO2 #undef XO3 #undef XO4 #undef ST #undef BLOCK static void xor_p5_mmx_2(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " movq %%mm0, (%1) ;\n" " pxor 8(%2), %%mm1 ;\n" " movq 24(%1), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " pxor 16(%2), %%mm2 ;\n" " movq 32(%1), %%mm4 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 24(%2), %%mm3 ;\n" " movq 40(%1), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%2), %%mm4 ;\n" " movq 48(%1), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 40(%2), %%mm5 ;\n" " movq 56(%1), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%2), %%mm6 ;\n" " pxor 56(%2), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2) : : "memory"); kernel_fpu_end(); } static void xor_p5_mmx_3(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor 8(%2), %%mm1 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 16(%2), %%mm2 ;\n" " movq %%mm0, (%1) ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor 16(%3), %%mm2 ;\n" " movq 24(%1), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " movq 32(%1), %%mm4 ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 24(%2), %%mm3 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 32(%2), %%mm4 ;\n" " pxor 24(%3), %%mm3 ;\n" " pxor 40(%2), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 40(%3), %%mm5 ;\n" " movq 48(%1), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " movq 56(%1), %%mm7 ;\n" " pxor 48(%2), %%mm6 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 56(%2), %%mm7 ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : : "memory" ); kernel_fpu_end(); } static void xor_p5_mmx_4(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor 8(%2), %%mm1 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 16(%2), %%mm2 ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor (%4), %%mm0 ;\n" " movq 24(%1), %%mm3 ;\n" " pxor 16(%3), %%mm2 ;\n" " pxor 8(%4), %%mm1 ;\n" " movq %%mm0, (%1) ;\n" " movq 32(%1), %%mm4 ;\n" " pxor 24(%2), %%mm3 ;\n" " pxor 16(%4), %%mm2 ;\n" " movq %%mm1, 8(%1) ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 32(%2), %%mm4 ;\n" " pxor 24(%3), %%mm3 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 40(%2), %%mm5 ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 24(%4), %%mm3 ;\n" " movq %%mm3, 24(%1) ;\n" " movq 56(%1), %%mm7 ;\n" " movq 48(%1), %%mm6 ;\n" " pxor 40(%3), %%mm5 ;\n" " pxor 32(%4), %%mm4 ;\n" " pxor 48(%2), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 56(%2), %%mm7 ;\n" " pxor 40(%4), %%mm5 ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%4), %%mm6 ;\n" " pxor 56(%4), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " addl $64, %4 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) : : "memory"); kernel_fpu_end(); } static void xor_p5_mmx_5(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4, const unsigned long * __restrict p5) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); /* Make sure GCC forgets anything it knows about p4 or p5, such that it won't pass to the asm volatile below a register that is shared with any other variable. That's because we modify p4 and p5 there, but we can't mark them as read/write, otherwise we'd overflow the 10-asm-operands limit of GCC < 3.1. */ asm("" : "+r" (p4), "+r" (p5)); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " pxor 8(%2), %%mm1 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor 16(%2), %%mm2 ;\n" " pxor (%4), %%mm0 ;\n" " pxor 8(%4), %%mm1 ;\n" " pxor 16(%3), %%mm2 ;\n" " movq 24(%1), %%mm3 ;\n" " pxor (%5), %%mm0 ;\n" " pxor 8(%5), %%mm1 ;\n" " movq %%mm0, (%1) ;\n" " pxor 16(%4), %%mm2 ;\n" " pxor 24(%2), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " pxor 16(%5), %%mm2 ;\n" " pxor 24(%3), %%mm3 ;\n" " movq 32(%1), %%mm4 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 24(%4), %%mm3 ;\n" " pxor 32(%2), %%mm4 ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 24(%5), %%mm3 ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 40(%2), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%4), %%mm4 ;\n" " pxor 40(%3), %%mm5 ;\n" " movq 48(%1), %%mm6 ;\n" " movq 56(%1), %%mm7 ;\n" " pxor 32(%5), %%mm4 ;\n" " pxor 40(%4), %%mm5 ;\n" " pxor 48(%2), %%mm6 ;\n" " pxor 56(%2), %%mm7 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " pxor 40(%5), %%mm5 ;\n" " pxor 48(%4), %%mm6 ;\n" " pxor 56(%4), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%5), %%mm6 ;\n" " pxor 56(%5), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " addl $64, %4 ;\n" " addl $64, %5 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : "r" (p4), "r" (p5) : "memory"); /* p4 and p5 were modified, and now the variables are dead. Clobber them just to be sure nobody does something stupid like assuming they have some legal value. */ asm("" : "=r" (p4), "=r" (p5)); kernel_fpu_end(); } static struct xor_block_template xor_block_pII_mmx = { .name = "pII_mmx", .do_2 = xor_pII_mmx_2, .do_3 = xor_pII_mmx_3, .do_4 = xor_pII_mmx_4, .do_5 = xor_pII_mmx_5, }; static struct xor_block_template xor_block_p5_mmx = { .name = "p5_mmx", .do_2 = xor_p5_mmx_2, .do_3 = xor_p5_mmx_3, .do_4 = xor_p5_mmx_4, .do_5 = xor_p5_mmx_5, }; static struct xor_block_template xor_block_pIII_sse = { .name = "pIII_sse", .do_2 = xor_sse_2, .do_3 = xor_sse_3, .do_4 = xor_sse_4, .do_5 = xor_sse_5, }; /* Also try the AVX routines */ #include <asm/xor_avx.h> /* Also try the generic routines. */ #include <asm-generic/xor.h> /* We force the use of the SSE xor block because it can write around L2. We may also be able to load into the L1 only depending on how the cpu deals with a load to a line that is being prefetched. */ #undef XOR_TRY_TEMPLATES #define XOR_TRY_TEMPLATES \ do { \ AVX_XOR_SPEED; \ if (boot_cpu_has(X86_FEATURE_XMM)) { \ xor_speed(&xor_block_pIII_sse); \ xor_speed(&xor_block_sse_pf64); \ } else if (boot_cpu_has(X86_FEATURE_MMX)) { \ xor_speed(&xor_block_pII_mmx); \ xor_speed(&xor_block_p5_mmx); \ } else { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_8regs_p); \ xor_speed(&xor_block_32regs); \ xor_speed(&xor_block_32regs_p); \ } \ } while (0) #endif /* _ASM_X86_XOR_32_H */ |