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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 | // SPDX-License-Identifier: MIT /* * Copyright 2014 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ /* * Authors: * Christian König <christian.koenig@amd.com> */ #include <linux/dma-fence-chain.h> #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" struct amdgpu_sync_entry { struct hlist_node node; struct dma_fence *fence; }; static struct kmem_cache *amdgpu_sync_slab; /** * amdgpu_sync_create - zero init sync object * * @sync: sync object to initialize * * Just clear the sync object for now. */ void amdgpu_sync_create(struct amdgpu_sync *sync) { hash_init(sync->fences); } /** * amdgpu_sync_same_dev - test if fence belong to us * * @adev: amdgpu device to use for the test * @f: fence to test * * Test if the fence was issued by us. */ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct dma_fence *f) { struct drm_sched_fence *s_fence = to_drm_sched_fence(f); if (s_fence) { struct amdgpu_ring *ring; ring = container_of(s_fence->sched, struct amdgpu_ring, sched); return ring->adev == adev; } return false; } /** * amdgpu_sync_get_owner - extract the owner of a fence * * @f: fence get the owner from * * Extract who originally created the fence. */ static void *amdgpu_sync_get_owner(struct dma_fence *f) { struct drm_sched_fence *s_fence; struct amdgpu_amdkfd_fence *kfd_fence; if (!f) return AMDGPU_FENCE_OWNER_UNDEFINED; s_fence = to_drm_sched_fence(f); if (s_fence) return s_fence->owner; kfd_fence = to_amdgpu_amdkfd_fence(f); if (kfd_fence) return AMDGPU_FENCE_OWNER_KFD; return AMDGPU_FENCE_OWNER_UNDEFINED; } /** * amdgpu_sync_keep_later - Keep the later fence * * @keep: existing fence to test * @fence: new fence * * Either keep the existing fence or the new one, depending which one is later. */ static void amdgpu_sync_keep_later(struct dma_fence **keep, struct dma_fence *fence) { if (*keep && dma_fence_is_later(*keep, fence)) return; dma_fence_put(*keep); *keep = dma_fence_get(fence); } /** * amdgpu_sync_add_later - add the fence to the hash * * @sync: sync object to add the fence to * @f: fence to add * * Tries to add the fence to an existing hash entry. Returns true when an entry * was found, false otherwise. */ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) { struct amdgpu_sync_entry *e; hash_for_each_possible(sync->fences, e, node, f->context) { if (unlikely(e->fence->context != f->context)) continue; amdgpu_sync_keep_later(&e->fence, f); return true; } return false; } /** * amdgpu_sync_fence - remember to sync to this fence * * @sync: sync object to add fence to * @f: fence to sync to * * Add the fence to the sync object. */ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f) { struct amdgpu_sync_entry *e; if (!f) return 0; if (amdgpu_sync_add_later(sync, f)) return 0; e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL); if (!e) return -ENOMEM; hash_add(sync->fences, &e->node, f->context); e->fence = dma_fence_get(f); return 0; } /* Determine based on the owner and mode if we should sync to a fence or not */ static bool amdgpu_sync_test_fence(struct amdgpu_device *adev, enum amdgpu_sync_mode mode, void *owner, struct dma_fence *f) { void *fence_owner = amdgpu_sync_get_owner(f); /* Always sync to moves, no matter what */ if (fence_owner == AMDGPU_FENCE_OWNER_UNDEFINED) return true; /* We only want to trigger KFD eviction fences on * evict or move jobs. Skip KFD fences otherwise. */ if (fence_owner == AMDGPU_FENCE_OWNER_KFD && owner != AMDGPU_FENCE_OWNER_UNDEFINED) return false; /* Never sync to VM updates either. */ if (fence_owner == AMDGPU_FENCE_OWNER_VM && owner != AMDGPU_FENCE_OWNER_UNDEFINED && owner != AMDGPU_FENCE_OWNER_KFD) return false; /* Ignore fences depending on the sync mode */ switch (mode) { case AMDGPU_SYNC_ALWAYS: return true; case AMDGPU_SYNC_NE_OWNER: if (amdgpu_sync_same_dev(adev, f) && fence_owner == owner) return false; break; case AMDGPU_SYNC_EQ_OWNER: if (amdgpu_sync_same_dev(adev, f) && fence_owner != owner) return false; break; case AMDGPU_SYNC_EXPLICIT: return false; } WARN(debug_evictions && fence_owner == AMDGPU_FENCE_OWNER_KFD, "Adding eviction fence to sync obj"); return true; } /** * amdgpu_sync_resv - sync to a reservation object * * @adev: amdgpu device * @sync: sync object to add fences from reservation object to * @resv: reservation object with embedded fence * @mode: how owner affects which fences we sync to * @owner: owner of the planned job submission * * Sync to the fence */ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, struct dma_resv *resv, enum amdgpu_sync_mode mode, void *owner) { struct dma_resv_iter cursor; struct dma_fence *f; int r; if (resv == NULL) return -EINVAL; /* TODO: Use DMA_RESV_USAGE_READ here */ dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, f) { dma_fence_chain_for_each(f, f) { struct dma_fence *tmp = dma_fence_chain_contained(f); if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) { r = amdgpu_sync_fence(sync, f); dma_fence_put(f); if (r) return r; break; } } } return 0; } /* Free the entry back to the slab */ static void amdgpu_sync_entry_free(struct amdgpu_sync_entry *e) { hash_del(&e->node); dma_fence_put(e->fence); kmem_cache_free(amdgpu_sync_slab, e); } /** * amdgpu_sync_peek_fence - get the next fence not signaled yet * * @sync: the sync object * @ring: optional ring to use for test * * Returns the next fence not signaled yet without removing it from the sync * object. */ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; int i; hash_for_each_safe(sync->fences, i, tmp, e, node) { struct dma_fence *f = e->fence; struct drm_sched_fence *s_fence = to_drm_sched_fence(f); if (dma_fence_is_signaled(f)) { amdgpu_sync_entry_free(e); continue; } if (ring && s_fence) { /* For fences from the same ring it is sufficient * when they are scheduled. */ if (s_fence->sched == &ring->sched) { if (dma_fence_is_signaled(&s_fence->scheduled)) continue; return &s_fence->scheduled; } } return f; } return NULL; } /** * amdgpu_sync_get_fence - get the next fence from the sync object * * @sync: sync object to use * * Get and removes the next fence from the sync object not signaled yet. */ struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; struct dma_fence *f; int i; hash_for_each_safe(sync->fences, i, tmp, e, node) { f = e->fence; hash_del(&e->node); kmem_cache_free(amdgpu_sync_slab, e); if (!dma_fence_is_signaled(f)) return f; dma_fence_put(f); } return NULL; } /** * amdgpu_sync_clone - clone a sync object * * @source: sync object to clone * @clone: pointer to destination sync object * * Adds references to all unsignaled fences in @source to @clone. Also * removes signaled fences from @source while at it. */ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; struct dma_fence *f; int i, r; hash_for_each_safe(source->fences, i, tmp, e, node) { f = e->fence; if (!dma_fence_is_signaled(f)) { r = amdgpu_sync_fence(clone, f); if (r) return r; } else { amdgpu_sync_entry_free(e); } } return 0; } /** * amdgpu_sync_push_to_job - push fences into job * @sync: sync object to get the fences from * @job: job to push the fences into * * Add all unsignaled fences from sync to job. */ int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; struct dma_fence *f; int i, r; hash_for_each_safe(sync->fences, i, tmp, e, node) { f = e->fence; if (dma_fence_is_signaled(f)) { amdgpu_sync_entry_free(e); continue; } dma_fence_get(f); r = drm_sched_job_add_dependency(&job->base, f); if (r) { dma_fence_put(f); return r; } } return 0; } int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; int i, r; hash_for_each_safe(sync->fences, i, tmp, e, node) { r = dma_fence_wait(e->fence, intr); if (r) return r; amdgpu_sync_entry_free(e); } return 0; } /** * amdgpu_sync_free - free the sync object * * @sync: sync object to use * * Free the sync object. */ void amdgpu_sync_free(struct amdgpu_sync *sync) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; unsigned int i; hash_for_each_safe(sync->fences, i, tmp, e, node) amdgpu_sync_entry_free(e); } /** * amdgpu_sync_init - init sync object subsystem * * Allocate the slab allocator. */ int amdgpu_sync_init(void) { amdgpu_sync_slab = kmem_cache_create( "amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0, SLAB_HWCACHE_ALIGN, NULL); if (!amdgpu_sync_slab) return -ENOMEM; return 0; } /** * amdgpu_sync_fini - fini sync object subsystem * * Free the slab allocator. */ void amdgpu_sync_fini(void) { kmem_cache_destroy(amdgpu_sync_slab); } |