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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2017~2018 NXP */ /dts-v1/; #include "imx8qxp.dtsi" #include <dt-bindings/usb/pd.h> / { model = "Freescale i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; chosen { stdout-path = &lpuart0; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x40000000>; }; reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; gpio-sbu-mux { compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec_mux>; select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; orientation-switch; port { usb3_data_ss: endpoint { remote-endpoint = <&typec_con_ss>; }; }; }; }; &dsp { status = "okay"; }; &dsp_reserved { status = "okay"; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; }; }; &i2c1 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; status = "okay"; i2c-mux@71 { compatible = "nxp,pca9646", "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; reg = <0x71>; reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; max7322: gpio@68 { compatible = "maxim,max7322"; reg = <0x68>; gpio-controller; #gpio-cells = <2>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; pca9557_a: gpio@1a { compatible = "nxp,pca9557"; reg = <0x1a>; gpio-controller; #gpio-cells = <2>; }; pca9557_b: gpio@1d { compatible = "nxp,pca9557"; reg = <0x1d>; gpio-controller; #gpio-cells = <2>; }; light-sensor@44 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isl29023>; compatible = "isil,isl29023"; reg = <0x44>; interrupt-parent = <&lsio_gpio1>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; }; }; }; ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; reg = <0x50>; interrupt-parent = <&lsio_gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; power-role = "source"; data-role = "dual"; source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; typec_dr_sw: endpoint { remote-endpoint = <&usb3_drd_sw>; }; }; port@1 { reg = <1>; typec_con_ss: endpoint { remote-endpoint = <&usb3_data_ss>; }; }; }; }; }; }; &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; &lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; status = "okay"; }; &lpuart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart3>; status = "okay"; }; &mu_m0 { status = "okay"; }; &mu1_m0 { status = "okay"; }; &scu_key { status = "okay"; }; &thermal_zones { pmic-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; trips { pmic_alert0: trip0 { temperature = <110000>; hysteresis = <2000>; type = "passive"; }; pmic_crit0: trip1 { temperature = <125000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&pmic_alert0>; cooling-device = <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; &usdhc1 { assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; non-removable; status = "okay"; }; &usdhc2 { assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; status = "okay"; }; &usb3_phy { status = "okay"; }; &usbotg3 { status = "okay"; }; &usbotg3_cdns3 { dr_mode = "otg"; usb-role-switch; status = "okay"; port { usb3_drd_sw: endpoint { remote-endpoint = <&typec_dr_sw>; }; }; }; &vpu { compatible = "nxp,imx8qxp-vpu"; status = "okay"; }; &vpu_core0 { reg = <0x2d040000 0x10000>; memory-region = <&decoder_boot>, <&decoder_rpc>; status = "okay"; }; &vpu_core1 { reg = <0x2d050000 0x10000>; memory-region = <&encoder_boot>, <&encoder_rpc>; status = "okay"; }; &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 >; }; pinctrl_ioexp_rst: ioexprstgrp { fsl,pins = < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 >; }; pinctrl_isl29023: isl29023grp { fsl,pins = < IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 >; }; pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 >; }; pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 >; }; pinctrl_lpuart2: lpuart2grp { fsl,pins = < IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 >; }; pinctrl_lpuart3: lpuart3grp { fsl,pins = < IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; pinctrl_typec: typecgrp { fsl,pins = < IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 >; }; pinctrl_typec_mux: typecmuxgrp { fsl,pins = < IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; }; |