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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 | /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> */ #ifndef __MTK_MDP3_COMP_H__ #define __MTK_MDP3_COMP_H__ #include "mtk-mdp3-cmdq.h" #define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...) \ cmdq_pkt_write_mask(&((cmd)->pkt), id, \ (base) + (ofst), (val), (mask), ##__VA_ARGS__) #define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...) \ do { \ typeof(mask) (m) = (mask); \ MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \ (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ (0xffffffff) : (m), ##__VA_ARGS__); \ } while (0) #define MM_REG_WAIT(cmd, evt) \ do { \ typeof(cmd) (c) = (cmd); \ typeof(evt) (e) = (evt); \ cmdq_pkt_wfe(&((c)->pkt), (e), true); \ } while (0) #define MM_REG_WAIT_NO_CLEAR(cmd, evt) \ do { \ typeof(cmd) (c) = (cmd); \ typeof(evt) (e) = (evt); \ cmdq_pkt_wfe(&((c)->pkt), (e), false); \ } while (0) #define MM_REG_CLEAR(cmd, evt) \ do { \ typeof(cmd) (c) = (cmd); \ typeof(evt) (e) = (evt); \ cmdq_pkt_clear_event(&((c)->pkt), (e)); \ } while (0) #define MM_REG_SET_EVENT(cmd, evt) \ do { \ typeof(cmd) (c) = (cmd); \ typeof(evt) (e) = (evt); \ cmdq_pkt_set_event(&((c)->pkt), (e)); \ } while (0) #define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...) \ do { \ typeof(_mask) (_m) = (_mask); \ cmdq_pkt_poll_mask(&((cmd)->pkt), id, \ (base) + (ofst), (val), (_m), ##__VA_ARGS__); \ } while (0) #define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...) \ do { \ typeof(mask) (m) = (mask); \ MM_REG_POLL_MASK((cmd), id, base, ofst, val, \ (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ (0xffffffff) : (m), ##__VA_ARGS__); \ } while (0) enum mtk_mdp_comp_id { MDP_COMP_NONE = -1, /* Invalid engine */ /* ISP */ MDP_COMP_WPEI = 0, MDP_COMP_WPEO, /* 1 */ MDP_COMP_WPEI2, /* 2 */ MDP_COMP_WPEO2, /* 3 */ MDP_COMP_ISP_IMGI, /* 4 */ MDP_COMP_ISP_IMGO, /* 5 */ MDP_COMP_ISP_IMG2O, /* 6 */ /* IPU */ MDP_COMP_IPUI, /* 7 */ MDP_COMP_IPUO, /* 8 */ /* MDP */ MDP_COMP_CAMIN, /* 9 */ MDP_COMP_CAMIN2, /* 10 */ MDP_COMP_RDMA0, /* 11 */ MDP_COMP_AAL0, /* 12 */ MDP_COMP_CCORR0, /* 13 */ MDP_COMP_RSZ0, /* 14 */ MDP_COMP_RSZ1, /* 15 */ MDP_COMP_TDSHP0, /* 16 */ MDP_COMP_COLOR0, /* 17 */ MDP_COMP_PATH0_SOUT, /* 18 */ MDP_COMP_PATH1_SOUT, /* 19 */ MDP_COMP_WROT0, /* 20 */ MDP_COMP_WDMA, /* 21 */ /* Dummy Engine */ MDP_COMP_RDMA1, /* 22 */ MDP_COMP_RSZ2, /* 23 */ MDP_COMP_TDSHP1, /* 24 */ MDP_COMP_WROT1, /* 25 */ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */ }; enum mdp_comp_type { MDP_COMP_TYPE_INVALID = 0, MDP_COMP_TYPE_RDMA, MDP_COMP_TYPE_RSZ, MDP_COMP_TYPE_WROT, MDP_COMP_TYPE_WDMA, MDP_COMP_TYPE_PATH, MDP_COMP_TYPE_TDSHP, MDP_COMP_TYPE_COLOR, MDP_COMP_TYPE_DRE, MDP_COMP_TYPE_CCORR, MDP_COMP_TYPE_HDR, MDP_COMP_TYPE_IMGI, MDP_COMP_TYPE_WPEI, MDP_COMP_TYPE_EXTO, /* External path */ MDP_COMP_TYPE_DL_PATH, /* Direct-link path */ MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */ }; #define MDP_GCE_NO_EVENT (-1) enum { MDP_GCE_EVENT_SOF = 0, MDP_GCE_EVENT_EOF = 1, MDP_GCE_EVENT_MAX, }; struct mdp_comp_match { enum mdp_comp_type type; u32 alias_id; s32 inner_id; }; /* Used to describe the item order in MDP property */ struct mdp_comp_info { u32 clk_num; u32 clk_ofst; u32 dts_reg_ofst; }; struct mdp_comp_data { struct mdp_comp_match match; struct mdp_comp_info info; }; struct mdp_comp_ops; struct mdp_comp { struct mdp_dev *mdp_dev; void __iomem *regs; phys_addr_t reg_base; u8 subsys_id; u8 clk_num; struct clk **clks; struct device *comp_dev; enum mdp_comp_type type; enum mtk_mdp_comp_id public_id; s32 inner_id; u32 alias_id; s32 gce_event[MDP_GCE_EVENT_MAX]; const struct mdp_comp_ops *ops; }; struct mdp_comp_ctx { struct mdp_comp *comp; const struct img_compparam *param; const struct img_input *input; const struct img_output *outputs[IMG_MAX_HW_OUTPUTS]; }; struct mdp_comp_ops { s64 (*get_comp_flag)(const struct mdp_comp_ctx *ctx); int (*init_comp)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd); int (*config_frame)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose); int (*config_subfrm)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index); int (*wait_comp_event)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd); int (*advance_subfrm)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index); int (*post_process)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd); }; struct mdp_dev; int mdp_comp_config(struct mdp_dev *mdp); void mdp_comp_destroy(struct mdp_dev *mdp); int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp); void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp); int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num); void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num); int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, const struct img_compparam *param, const struct img_ipi_frameparam *frame); #endif /* __MTK_MDP3_COMP_H__ */ |