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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: | Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory Controller device maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - Lukasz Luba <lukasz.luba@arm.com> description: | The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM memory chips are connected. The driver is to monitor the controller in runtime and switch frequency and voltage. To monitor the usage of the controller in runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which is able to measure the current load of the memory. When 'userspace' governor is used for the driver, an application is able to switch the DMC and memory frequency. properties: compatible: items: - const: samsung,exynos5422-dmc clock-names: items: - const: fout_spll - const: mout_sclk_spll - const: ff_dout_spll2 - const: fout_bpll - const: mout_bpll - const: sclk_bpll - const: mout_mx_mspll_ccore - const: mout_mclk_cdrex clocks: minItems: 8 maxItems: 8 devfreq-events: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 16 items: maxItems: 1 description: phandles of the PPMU events used by the controller. device-handle: $ref: /schemas/types.yaml#/definitions/phandle description: | phandle of the connected DRAM memory device. For more information please refer to jedec,lpddr3.yaml. operating-points-v2: true interrupts: items: - description: DMC internal performance event counters in DREX0 - description: DMC internal performance event counters in DREX1 interrupt-names: items: - const: drex_0 - const: drex_1 reg: items: - description: registers of DREX0 - description: registers of DREX1 samsung,syscon-clk: $ref: /schemas/types.yaml#/definitions/phandle description: | Phandle of the clock register set used by the controller, these registers are used for enabling a 'pause' feature and are not exposed by clock framework but they must be used in a safe way. The register offsets are in the driver code and specyfic for this SoC type. vdd-supply: true required: - compatible - clock-names - clocks - devfreq-events - device-handle - reg - samsung,syscon-clk additionalProperties: false examples: - | #include <dt-bindings/clock/exynos5420.h> ppmu_dmc0_0: ppmu@10d00000 { compatible = "samsung,exynos-ppmu"; reg = <0x10d00000 0x2000>; clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; clock-names = "ppmu"; events { ppmu_event_dmc0_0: ppmu-event3-dmc0-0 { event-name = "ppmu-event3-dmc0_0"; }; }; }; memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, <&clock CLK_FOUT_BPLL>, <&clock CLK_MOUT_BPLL>, <&clock CLK_SCLK_BPLL>, <&clock CLK_MOUT_MX_MSPLL_CCORE>, <&clock CLK_MOUT_MCLK_CDREX>; clock-names = "fout_spll", "mout_sclk_spll", "ff_dout_spll2", "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; interrupt-parent = <&combiner>; interrupts = <16 0>, <16 1>; interrupt-names = "drex_0", "drex_1"; }; |