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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 | /* SPDX-License-Identifier: ISC */ /* Copyright (C) 2020 MediaTek Inc. * * Author: Sean Wang <sean.wang@mediatek.com> */ #ifndef __MT76S_H #define __MT76S_H #define MT_PSE_PAGE_SZ 128 #define MCR_WCIR 0x0000 #define MCR_WHLPCR 0x0004 #define WHLPCR_FW_OWN_REQ_CLR BIT(9) #define WHLPCR_FW_OWN_REQ_SET BIT(8) #define WHLPCR_IS_DRIVER_OWN BIT(8) #define WHLPCR_INT_EN_CLR BIT(1) #define WHLPCR_INT_EN_SET BIT(0) #define MCR_WSDIOCSR 0x0008 #define MCR_WHCR 0x000C #define W_INT_CLR_CTRL BIT(1) #define RECV_MAILBOX_RD_CLR_EN BIT(2) #define WF_SYS_RSTB BIT(4) /* supported in CONNAC2 */ #define WF_WHOLE_PATH_RSTB BIT(5) /* supported in CONNAC2 */ #define WF_SDIO_WF_PATH_RSTB BIT(6) /* supported in CONNAC2 */ #define MAX_HIF_RX_LEN_NUM GENMASK(13, 8) #define MAX_HIF_RX_LEN_NUM_CONNAC2 GENMASK(14, 8) /* supported in CONNAC2 */ #define WF_RST_DONE BIT(15) /* supported in CONNAC2 */ #define RX_ENHANCE_MODE BIT(16) #define MCR_WHISR 0x0010 #define MCR_WHIER 0x0014 #define WHIER_D2H_SW_INT GENMASK(31, 8) #define WHIER_FW_OWN_BACK_INT_EN BIT(7) #define WHIER_ABNORMAL_INT_EN BIT(6) #define WHIER_WDT_INT_EN BIT(5) /* supported in CONNAC2 */ #define WHIER_RX1_DONE_INT_EN BIT(2) #define WHIER_RX0_DONE_INT_EN BIT(1) #define WHIER_TX_DONE_INT_EN BIT(0) #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \ WHIER_RX1_DONE_INT_EN | \ WHIER_TX_DONE_INT_EN | \ WHIER_ABNORMAL_INT_EN | \ WHIER_D2H_SW_INT) #define MCR_WASR 0x0020 #define MCR_WSICR 0x0024 #define MCR_WTSR0 0x0028 #define TQ0_CNT GENMASK(7, 0) #define TQ1_CNT GENMASK(15, 8) #define TQ2_CNT GENMASK(23, 16) #define TQ3_CNT GENMASK(31, 24) #define MCR_WTSR1 0x002c #define TQ4_CNT GENMASK(7, 0) #define TQ5_CNT GENMASK(15, 8) #define TQ6_CNT GENMASK(23, 16) #define TQ7_CNT GENMASK(31, 24) #define MCR_WTDR1 0x0034 #define MCR_WRDR0 0x0050 #define MCR_WRDR1 0x0054 #define MCR_WRDR(p) (0x0050 + 4 * (p)) #define MCR_H2DSM0R 0x0070 #define H2D_SW_INT_READ BIT(16) #define H2D_SW_INT_WRITE BIT(17) #define H2D_SW_INT_CLEAR_MAILBOX_ACK BIT(22) #define MCR_H2DSM1R 0x0074 #define MCR_D2HRM0R 0x0078 #define MCR_D2HRM1R 0x007c #define MCR_D2HRM2R 0x0080 #define MCR_WRPLR 0x0090 #define RX0_PACKET_LENGTH GENMASK(15, 0) #define RX1_PACKET_LENGTH GENMASK(31, 16) #define MCR_WTMDR 0x00b0 #define MCR_WTMCR 0x00b4 #define MCR_WTMDPCR0 0x00b8 #define MCR_WTMDPCR1 0x00bc #define MCR_WPLRCR 0x00d4 #define MCR_WSR 0x00D8 #define MCR_CLKIOCR 0x0100 #define MCR_CMDIOCR 0x0104 #define MCR_DAT0IOCR 0x0108 #define MCR_DAT1IOCR 0x010C #define MCR_DAT2IOCR 0x0110 #define MCR_DAT3IOCR 0x0114 #define MCR_CLKDLYCR 0x0118 #define MCR_CMDDLYCR 0x011C #define MCR_ODATDLYCR 0x0120 #define MCR_IDATDLYCR1 0x0124 #define MCR_IDATDLYCR2 0x0128 #define MCR_ILCHCR 0x012C #define MCR_WTQCR0 0x0130 #define MCR_WTQCR1 0x0134 #define MCR_WTQCR2 0x0138 #define MCR_WTQCR3 0x013C #define MCR_WTQCR4 0x0140 #define MCR_WTQCR5 0x0144 #define MCR_WTQCR6 0x0148 #define MCR_WTQCR7 0x014C #define MCR_WTQCR(x) (0x130 + 4 * (x)) #define TXQ_CNT_L GENMASK(15, 0) #define TXQ_CNT_H GENMASK(31, 16) #define MCR_SWPCDBGR 0x0154 #define MCR_H2DSM2R 0x0160 /* supported in CONNAC2 */ #define MCR_H2DSM3R 0x0164 /* supported in CONNAC2 */ #define MCR_D2HRM3R 0x0174 /* supported in CONNAC2 */ #define D2HRM3R_IS_DRIVER_OWN BIT(0) #define MCR_WTQCR8 0x0190 /* supported in CONNAC2 */ #define MCR_WTQCR9 0x0194 /* supported in CONNAC2 */ #define MCR_WTQCR10 0x0198 /* supported in CONNAC2 */ #define MCR_WTQCR11 0x019C /* supported in CONNAC2 */ #define MCR_WTQCR12 0x01A0 /* supported in CONNAC2 */ #define MCR_WTQCR13 0x01A4 /* supported in CONNAC2 */ #define MCR_WTQCR14 0x01A8 /* supported in CONNAC2 */ #define MCR_WTQCR15 0x01AC /* supported in CONNAC2 */ enum mt76_connac_sdio_ver { MT76_CONNAC_SDIO, MT76_CONNAC2_SDIO, }; struct mt76s_intr { u32 isr; u32 *rec_mb; struct { u32 *wtqcr; } tx; struct { u16 *len[2]; u16 *num; } rx; }; #endif |