Linux Audio
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Embedded Linux Audio
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/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_ROT0_MASKS_H_ #define ASIC_REG_ROT0_MASKS_H_ /* ***************************************** * ROT0 * (Prototype: ROTATOR) ***************************************** */ /* ROT0_KMD_MODE */ #define ROT0_KMD_MODE_EN_SHIFT 0 #define ROT0_KMD_MODE_EN_MASK 0x1 /* ROT0_CPL_QUEUE_EN */ #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1 /* ROT0_CPL_QUEUE_ADDR_L */ #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF /* ROT0_CPL_QUEUE_ADDR_H */ #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF /* ROT0_CPL_QUEUE_DATA */ #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF /* ROT0_CPL_QUEUE_AWUSER */ #define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0 #define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF /* ROT0_CPL_QUEUE_AXI */ #define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0 #define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF #define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4 #define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70 /* ROT0_CPL_MSG_THRESHOLD */ #define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0 #define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F /* ROT0_CPL_MSG_AXI */ #define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0 #define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF #define ROT0_CPL_MSG_AXI_PROT_SHIFT 4 #define ROT0_CPL_MSG_AXI_PROT_MASK 0x70 /* ROT0_AXI_WB */ #define ROT0_AXI_WB_CACHE_SHIFT 0 #define ROT0_AXI_WB_CACHE_MASK 0xF #define ROT0_AXI_WB_PROT_SHIFT 4 #define ROT0_AXI_WB_PROT_MASK 0x70 /* ROT0_ERR_CFG */ #define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0 #define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1 /* ROT0_ERR_STATUS */ #define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0 #define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1 #define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1 #define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2 #define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2 #define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4 #define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3 #define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8 #define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4 #define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10 /* ROT0_WBC_MAX_OUTSTANDING */ #define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0 #define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF /* ROT0_WBC_RL */ #define ROT0_WBC_RL_SATURATION_SHIFT 0 #define ROT0_WBC_RL_SATURATION_MASK 0xFF #define ROT0_WBC_RL_TIMEOUT_SHIFT 8 #define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00 #define ROT0_WBC_RL_RST_TOKEN_SHIFT 16 #define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000 #define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24 #define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000 /* ROT0_WBC_INFLIGHTS */ #define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0 #define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF /* ROT0_WBC_INFO */ #define ROT0_WBC_INFO_EMPTY_SHIFT 0 #define ROT0_WBC_INFO_EMPTY_MASK 0x1 #define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1 #define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2 /* ROT0_WBC_MON */ #define ROT0_WBC_MON_CNT_SHIFT 0 #define ROT0_WBC_MON_CNT_MASK 0x1 #define ROT0_WBC_MON_TS_SHIFT 8 #define ROT0_WBC_MON_TS_MASK 0x300 #define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16 #define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000 /* ROT0_RSB_CAM_MAX_SIZE */ #define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0 #define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF #define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16 #define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 /* ROT0_RSB_CFG */ #define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0 #define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1 #define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1 #define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2 /* ROT0_RSB_MAX_OS */ #define ROT0_RSB_MAX_OS_VAL_SHIFT 0 #define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF /* ROT0_RSB_RL */ #define ROT0_RSB_RL_SATURATION_SHIFT 0 #define ROT0_RSB_RL_SATURATION_MASK 0xFF #define ROT0_RSB_RL_TIMEOUT_SHIFT 8 #define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00 #define ROT0_RSB_RL_RST_TOKEN_SHIFT 16 #define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000 #define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24 #define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000 /* ROT0_RSB_INFLIGHTS */ #define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0 #define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF /* ROT0_RSB_OCCUPANCY */ #define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0 #define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF /* ROT0_RSB_INFO */ #define ROT0_RSB_INFO_EMPTY_SHIFT 0 #define ROT0_RSB_INFO_EMPTY_MASK 0x1 #define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1 #define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2 /* ROT0_RSB_MON */ #define ROT0_RSB_MON_CNT_SHIFT 0 #define ROT0_RSB_MON_CNT_MASK 0x1FFF #define ROT0_RSB_MON_TS_SHIFT 16 #define ROT0_RSB_MON_TS_MASK 0x30000 /* ROT0_RSB_MON_CONTEXT_ID */ #define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0 #define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF /* ROT0_MSS_HALT */ #define ROT0_MSS_HALT_VAL_SHIFT 0 #define ROT0_MSS_HALT_VAL_MASK 0x7 /* ROT0_MSS_SEI_STATUS */ #define ROT0_MSS_SEI_STATUS_I0_SHIFT 0 #define ROT0_MSS_SEI_STATUS_I0_MASK 0x1 #define ROT0_MSS_SEI_STATUS_I1_SHIFT 1 #define ROT0_MSS_SEI_STATUS_I1_MASK 0x2 #define ROT0_MSS_SEI_STATUS_I2_SHIFT 2 #define ROT0_MSS_SEI_STATUS_I2_MASK 0x4 #define ROT0_MSS_SEI_STATUS_I3_SHIFT 3 #define ROT0_MSS_SEI_STATUS_I3_MASK 0x8 #define ROT0_MSS_SEI_STATUS_I4_SHIFT 4 #define ROT0_MSS_SEI_STATUS_I4_MASK 0x10 #define ROT0_MSS_SEI_STATUS_I5_SHIFT 5 #define ROT0_MSS_SEI_STATUS_I5_MASK 0x20 #define ROT0_MSS_SEI_STATUS_I6_SHIFT 6 #define ROT0_MSS_SEI_STATUS_I6_MASK 0x40 #define ROT0_MSS_SEI_STATUS_I7_SHIFT 7 #define ROT0_MSS_SEI_STATUS_I7_MASK 0x80 #define ROT0_MSS_SEI_STATUS_I8_SHIFT 8 #define ROT0_MSS_SEI_STATUS_I8_MASK 0x100 #define ROT0_MSS_SEI_STATUS_I9_SHIFT 9 #define ROT0_MSS_SEI_STATUS_I9_MASK 0x200 #define ROT0_MSS_SEI_STATUS_I10_SHIFT 10 #define ROT0_MSS_SEI_STATUS_I10_MASK 0x400 #define ROT0_MSS_SEI_STATUS_I11_SHIFT 11 #define ROT0_MSS_SEI_STATUS_I11_MASK 0x800 #define ROT0_MSS_SEI_STATUS_I12_SHIFT 12 #define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000 #define ROT0_MSS_SEI_STATUS_I13_SHIFT 13 #define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000 #define ROT0_MSS_SEI_STATUS_I14_SHIFT 14 #define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000 #define ROT0_MSS_SEI_STATUS_I15_SHIFT 15 #define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000 #define ROT0_MSS_SEI_STATUS_I16_SHIFT 16 #define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000 #define ROT0_MSS_SEI_STATUS_I17_SHIFT 17 #define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000 #define ROT0_MSS_SEI_STATUS_I18_SHIFT 18 #define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000 #define ROT0_MSS_SEI_STATUS_I19_SHIFT 19 #define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000 #define ROT0_MSS_SEI_STATUS_I20_SHIFT 20 #define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000 #define ROT0_MSS_SEI_STATUS_I21_SHIFT 21 #define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000 /* ROT0_MSS_SEI_MASK */ #define ROT0_MSS_SEI_MASK_VAL_SHIFT 0 #define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF /* ROT0_MSS_SPI_STATUS */ #define ROT0_MSS_SPI_STATUS_I0_SHIFT 0 #define ROT0_MSS_SPI_STATUS_I0_MASK 0x1 #define ROT0_MSS_SPI_STATUS_I1_SHIFT 1 #define ROT0_MSS_SPI_STATUS_I1_MASK 0x2 #define ROT0_MSS_SPI_STATUS_I2_SHIFT 2 #define ROT0_MSS_SPI_STATUS_I2_MASK 0x4 #define ROT0_MSS_SPI_STATUS_I3_SHIFT 3 #define ROT0_MSS_SPI_STATUS_I3_MASK 0x8 #define ROT0_MSS_SPI_STATUS_I4_SHIFT 4 #define ROT0_MSS_SPI_STATUS_I4_MASK 0x10 #define ROT0_MSS_SPI_STATUS_I5_SHIFT 5 #define ROT0_MSS_SPI_STATUS_I5_MASK 0x20 #define ROT0_MSS_SPI_STATUS_I6_SHIFT 6 #define ROT0_MSS_SPI_STATUS_I6_MASK 0x40 #define ROT0_MSS_SPI_STATUS_I7_SHIFT 7 #define ROT0_MSS_SPI_STATUS_I7_MASK 0x80 /* ROT0_MSS_SPI_MASK */ #define ROT0_MSS_SPI_MASK_VAL_SHIFT 0 #define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF /* ROT0_DISABLE_PAD_CALC */ #define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0 #define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3 /* ROT0_QMAN_CFG */ #define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0 #define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1 /* ROT0_CLK_EN */ #define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0 #define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1 #define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4 #define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10 #define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5 #define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20 /* ROT0_MRSB_CAM_MAX_SIZE */ #define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0 #define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF #define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16 #define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 /* ROT0_MRSB_CFG */ #define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0 #define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1 #define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1 #define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2 /* ROT0_MRSB_MAX_OS */ #define ROT0_MRSB_MAX_OS_VAL_SHIFT 0 #define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF /* ROT0_MRSB_RL */ #define ROT0_MRSB_RL_SATURATION_SHIFT 0 #define ROT0_MRSB_RL_SATURATION_MASK 0xFF #define ROT0_MRSB_RL_TIMEOUT_SHIFT 8 #define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00 #define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16 #define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000 #define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24 #define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000 /* ROT0_MRSB_INFLIGHTS */ #define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0 #define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF /* ROT0_MRSB_OCCUPANCY */ #define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0 #define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF /* ROT0_MRSB_INFO */ #define ROT0_MRSB_INFO_EMPTY_SHIFT 0 #define ROT0_MRSB_INFO_EMPTY_MASK 0x1 #define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1 #define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2 /* ROT0_MRSB_MON */ #define ROT0_MRSB_MON_CNT_SHIFT 0 #define ROT0_MRSB_MON_CNT_MASK 0x1FFF #define ROT0_MRSB_MON_TS_SHIFT 16 #define ROT0_MRSB_MON_TS_MASK 0x30000 /* ROT0_MRSB_MON_CONTEXT_ID */ #define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0 #define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF /* ROT0_MSS_STS */ #define ROT0_MSS_STS_IS_HALT_SHIFT 0 #define ROT0_MSS_STS_IS_HALT_MASK 0x1 #endif /* ASIC_REG_ROT0_MASKS_H_ */
