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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 | /* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_DISPLAY_LIMITS_H__ #define __INTEL_DISPLAY_LIMITS_H__ /* * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the * rest have consecutive values and match the enum values of transcoders * with a 1:1 transcoder -> pipe mapping. */ enum pipe { INVALID_PIPE = -1, PIPE_A = 0, PIPE_B, PIPE_C, PIPE_D, _PIPE_EDP, I915_MAX_PIPES = _PIPE_EDP }; enum transcoder { INVALID_TRANSCODER = -1, /* * The following transcoders have a 1:1 transcoder -> pipe mapping, * keep their values fixed: the code assumes that TRANSCODER_A=0, the * rest have consecutive values and match the enum values of the pipes * they map to. */ TRANSCODER_A = PIPE_A, TRANSCODER_B = PIPE_B, TRANSCODER_C = PIPE_C, TRANSCODER_D = PIPE_D, /* * The following transcoders can map to any pipe, their enum value * doesn't need to stay fixed. */ TRANSCODER_EDP, TRANSCODER_DSI_0, TRANSCODER_DSI_1, TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ I915_MAX_TRANSCODERS }; /* * Per-pipe plane identifier. * I915_MAX_PLANES in the enum below is the maximum (across all platforms) * number of planes per CRTC. Not all platforms really have this many planes, * which means some arrays of size I915_MAX_PLANES may have unused entries * between the topmost sprite plane and the cursor plane. * * This is expected to be passed to various register macros * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. */ enum plane_id { PLANE_PRIMARY, PLANE_SPRITE0, PLANE_SPRITE1, PLANE_SPRITE2, PLANE_SPRITE3, PLANE_SPRITE4, PLANE_SPRITE5, PLANE_CURSOR, I915_MAX_PLANES, }; enum port { PORT_NONE = -1, PORT_A = 0, PORT_B, PORT_C, PORT_D, PORT_E, PORT_F, PORT_G, PORT_H, PORT_I, /* tgl+ */ PORT_TC1 = PORT_D, PORT_TC2, PORT_TC3, PORT_TC4, PORT_TC5, PORT_TC6, /* XE_LPD repositions D/E offsets and bitfields */ PORT_D_XELPD = PORT_TC5, PORT_E_XELPD, I915_MAX_PORTS }; enum hpd_pin { HPD_NONE = 0, HPD_TV = HPD_NONE, /* TV is known to be unreliable */ HPD_CRT, HPD_SDVO_B, HPD_SDVO_C, HPD_PORT_A, HPD_PORT_B, HPD_PORT_C, HPD_PORT_D, HPD_PORT_E, HPD_PORT_TC1, HPD_PORT_TC2, HPD_PORT_TC3, HPD_PORT_TC4, HPD_PORT_TC5, HPD_PORT_TC6, HPD_NUM_PINS }; #endif /* __INTEL_DISPLAY_LIMITS_H__ */ |