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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 | // SPDX-License-Identifier: GPL-2.0 /* * s390 specific pci instructions * * Copyright IBM Corp. 2013 */ #include <linux/export.h> #include <linux/errno.h> #include <linux/delay.h> #include <linux/jump_label.h> #include <asm/asm-extable.h> #include <asm/facility.h> #include <asm/pci_insn.h> #include <asm/pci_debug.h> #include <asm/pci_io.h> #include <asm/processor.h> #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */ struct zpci_err_insn_data { u8 insn; u8 cc; u8 status; union { struct { u64 req; u64 offset; }; struct { u64 addr; u64 len; }; }; } __packed; static inline void zpci_err_insn_req(int lvl, u8 insn, u8 cc, u8 status, u64 req, u64 offset) { struct zpci_err_insn_data data = { .insn = insn, .cc = cc, .status = status, .req = req, .offset = offset}; zpci_err_hex_level(lvl, &data, sizeof(data)); } static inline void zpci_err_insn_addr(int lvl, u8 insn, u8 cc, u8 status, u64 addr, u64 len) { struct zpci_err_insn_data data = { .insn = insn, .cc = cc, .status = status, .addr = addr, .len = len}; zpci_err_hex_level(lvl, &data, sizeof(data)); } /* Modify PCI Function Controls */ static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status) { u8 cc; asm volatile ( " .insn rxy,0xe300000000d0,%[req],%[fib]\n" " ipm %[cc]\n" " srl %[cc],28\n" : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib) : : "cc"); *status = req >> 24 & 0xff; return cc; } u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status) { bool retried = false; u8 cc; do { cc = __mpcifc(req, fib, status); if (cc == 2) { msleep(ZPCI_INSN_BUSY_DELAY); if (!retried) { zpci_err_insn_req(1, 'M', cc, *status, req, 0); retried = true; } } } while (cc == 2); if (cc) zpci_err_insn_req(0, 'M', cc, *status, req, 0); else if (retried) zpci_err_insn_req(1, 'M', cc, *status, req, 0); return cc; } EXPORT_SYMBOL_GPL(zpci_mod_fc); /* Refresh PCI Translations */ static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status) { union register_pair addr_range = {.even = addr, .odd = range}; u8 cc; asm volatile ( " .insn rre,0xb9d30000,%[fn],%[addr_range]\n" " ipm %[cc]\n" " srl %[cc],28\n" : [cc] "=d" (cc), [fn] "+d" (fn) : [addr_range] "d" (addr_range.pair) : "cc"); *status = fn >> 24 & 0xff; return cc; } int zpci_refresh_trans(u64 fn, u64 addr, u64 range) { bool retried = false; u8 cc, status; do { cc = __rpcit(fn, addr, range, &status); if (cc == 2) { udelay(ZPCI_INSN_BUSY_DELAY); if (!retried) { zpci_err_insn_addr(1, 'R', cc, status, addr, range); retried = true; } } } while (cc == 2); if (cc) zpci_err_insn_addr(0, 'R', cc, status, addr, range); else if (retried) zpci_err_insn_addr(1, 'R', cc, status, addr, range); if (cc == 1 && (status == 4 || status == 16)) return -ENOMEM; return (cc) ? -EIO : 0; } /* Set Interruption Controls */ int zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib) { if (!test_facility(72)) return -EIO; asm volatile( ".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n" : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib)); return 0; } EXPORT_SYMBOL_GPL(zpci_set_irq_ctrl); /* PCI Load */ static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status) { union register_pair req_off = {.even = req, .odd = offset}; int cc = -ENXIO; u64 __data; asm volatile ( " .insn rre,0xb9d20000,%[data],%[req_off]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [data] "=d" (__data), [req_off] "+&d" (req_off.pair) :: "cc"); *status = req_off.even >> 24 & 0xff; *data = __data; return cc; } static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status) { u64 __data; int cc; cc = ____pcilg(&__data, req, offset, status); if (!cc) *data = __data; return cc; } int __zpci_load(u64 *data, u64 req, u64 offset) { bool retried = false; u8 status; int cc; do { cc = __pcilg(data, req, offset, &status); if (cc == 2) { udelay(ZPCI_INSN_BUSY_DELAY); if (!retried) { zpci_err_insn_req(1, 'l', cc, status, req, offset); retried = true; } } } while (cc == 2); if (cc) zpci_err_insn_req(0, 'l', cc, status, req, offset); else if (retried) zpci_err_insn_req(1, 'l', cc, status, req, offset); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(__zpci_load); static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr, unsigned long len) { struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)]; u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len); return __zpci_load(data, req, ZPCI_OFFSET(addr)); } static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status) { union register_pair ioaddr_len = {.even = ioaddr, .odd = len}; int cc = -ENXIO; u64 __data; asm volatile ( " .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [data] "=d" (__data), [ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc"); *status = ioaddr_len.odd >> 24 & 0xff; *data = __data; return cc; } int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len) { u8 status; int cc; if (!static_branch_unlikely(&have_mio)) return zpci_load_fh(data, addr, len); cc = __pcilg_mio(data, (__force u64) addr, len, &status); if (cc) zpci_err_insn_addr(0, 'L', cc, status, (__force u64) addr, len); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(zpci_load); /* PCI Store */ static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status) { union register_pair req_off = {.even = req, .odd = offset}; int cc = -ENXIO; asm volatile ( " .insn rre,0xb9d00000,%[data],%[req_off]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [req_off] "+&d" (req_off.pair) : [data] "d" (data) : "cc"); *status = req_off.even >> 24 & 0xff; return cc; } int __zpci_store(u64 data, u64 req, u64 offset) { bool retried = false; u8 status; int cc; do { cc = __pcistg(data, req, offset, &status); if (cc == 2) { udelay(ZPCI_INSN_BUSY_DELAY); if (!retried) { zpci_err_insn_req(1, 's', cc, status, req, offset); retried = true; } } } while (cc == 2); if (cc) zpci_err_insn_req(0, 's', cc, status, req, offset); else if (retried) zpci_err_insn_req(1, 's', cc, status, req, offset); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(__zpci_store); static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data, unsigned long len) { struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)]; u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len); return __zpci_store(data, req, ZPCI_OFFSET(addr)); } static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status) { union register_pair ioaddr_len = {.even = ioaddr, .odd = len}; int cc = -ENXIO; asm volatile ( " .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair) : [data] "d" (data) : "cc", "memory"); *status = ioaddr_len.odd >> 24 & 0xff; return cc; } int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len) { u8 status; int cc; if (!static_branch_unlikely(&have_mio)) return zpci_store_fh(addr, data, len); cc = __pcistg_mio(data, (__force u64) addr, len, &status); if (cc) zpci_err_insn_addr(0, 'S', cc, status, (__force u64) addr, len); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(zpci_store); /* PCI Store Block */ static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status) { int cc = -ENXIO; asm volatile ( " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [req] "+d" (req) : [offset] "d" (offset), [data] "Q" (*data) : "cc"); *status = req >> 24 & 0xff; return cc; } int __zpci_store_block(const u64 *data, u64 req, u64 offset) { bool retried = false; u8 status; int cc; do { cc = __pcistb(data, req, offset, &status); if (cc == 2) { udelay(ZPCI_INSN_BUSY_DELAY); if (!retried) { zpci_err_insn_req(0, 'b', cc, status, req, offset); retried = true; } } } while (cc == 2); if (cc) zpci_err_insn_req(0, 'b', cc, status, req, offset); else if (retried) zpci_err_insn_req(1, 'b', cc, status, req, offset); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(__zpci_store_block); static inline int zpci_write_block_fh(volatile void __iomem *dst, const void *src, unsigned long len) { struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)]; u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len); u64 offset = ZPCI_OFFSET(dst); return __zpci_store_block(src, req, offset); } static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status) { int cc = -ENXIO; asm volatile ( " .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n" "0: ipm %[cc]\n" " srl %[cc],28\n" "1:\n" EX_TABLE(0b, 1b) : [cc] "+d" (cc), [len] "+d" (len) : [ioaddr] "d" (ioaddr), [data] "Q" (*data) : "cc"); *status = len >> 24 & 0xff; return cc; } int zpci_write_block(volatile void __iomem *dst, const void *src, unsigned long len) { u8 status; int cc; if (!static_branch_unlikely(&have_mio)) return zpci_write_block_fh(dst, src, len); cc = __pcistb_mio(src, (__force u64) dst, len, &status); if (cc) zpci_err_insn_addr(0, 'B', cc, status, (__force u64) dst, len); return (cc > 0) ? -EIO : cc; } EXPORT_SYMBOL_GPL(zpci_write_block); static inline void __pciwb_mio(void) { asm volatile (".insn rre,0xb9d50000,0,0\n"); } void zpci_barrier(void) { if (static_branch_likely(&have_mio)) __pciwb_mio(); } EXPORT_SYMBOL_GPL(zpci_barrier); |