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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 | // SPDX-License-Identifier: GPL-2.0-or-later /* * P1021 MDS Device Tree Source * * Copyright 2010,2012 Freescale Semiconductor Inc. */ /include/ "p1021si-pre.dtsi" / { model = "fsl,P1021"; compatible = "fsl,P1021MDS"; aliases { ethernet3 = &enet3; ethernet4 = &enet4; }; memory { device_type = "memory"; }; lbc: localbus@ffe05000 { reg = <0x0 0xffe05000 0x0 0x1000>; /* NAND Flash, BCSR, PMC0/1*/ ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 0x1 0x0 0x0 0xf8000000 0x00008000 0x2 0x0 0x0 0xf8010000 0x00020000 0x3 0x0 0x0 0xf8020000 0x00020000>; nand@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1021-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x0 0x0 0x40000>; partition@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; label = "NAND (RO) U-Boot Image"; read-only; }; partition@100000 { /* 1MB for DTB Image */ reg = <0x00100000 0x00100000>; label = "NAND (RO) DTB Image"; read-only; }; partition@200000 { /* 4MB for Linux Kernel Image */ reg = <0x00200000 0x00400000>; label = "NAND (RO) Linux Kernel Image"; read-only; }; partition@600000 { /* 5MB for Compressed Root file System Image */ reg = <0x00600000 0x00500000>; label = "NAND (RO) Compressed RFS Image"; read-only; }; partition@b00000 { /* 6MB for JFFS2 based Root file System */ reg = <0x00a00000 0x00600000>; label = "NAND (RW) JFFS2 Root File System"; }; partition@1100000 { /* 14MB for JFFS2 based Root file System */ reg = <0x01100000 0x00e00000>; label = "NAND (RW) Writable User area"; }; partition@1f00000 { /* 1MB for microcode */ reg = <0x01f00000 0x00100000>; label = "NAND (RO) QE Ucode"; read-only; }; }; bcsr@1,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1021mds-bcsr"; reg = <1 0 0x8000>; ranges = <0 1 0 0x8000>; }; pib@2,0 { compatible = "fsl,p1021mds-pib"; reg = <2 0 0x10000>; }; pib@3,0 { compatible = "fsl,p1021mds-pib"; reg = <3 0 0x10000>; }; }; soc: soc@ffe00000 { compatible = "fsl,p1021-immr", "simple-bus"; ranges = <0x0 0x0 0xffe00000 0x100000>; i2c@3000 { rtc@68 { compatible = "dallas,ds1374"; reg = <0x68>; }; }; spi@7000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25sl12801", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; /* input clock */ partition@u-boot { label = "u-boot-spi"; reg = <0x00000000 0x00100000>; read-only; }; partition@kernel { label = "kernel-spi"; reg = <0x00100000 0x00500000>; read-only; }; partition@dtb { label = "dtb-spi"; reg = <0x00600000 0x00100000>; read-only; }; partition@fs { label = "file system-spi"; reg = <0x00700000 0x00900000>; }; }; }; usb@22000 { phy_type = "ulpi"; dr_mode = "host"; }; mdio@24000 { phy0: ethernet-phy@0 { interrupts = <1 1 0 0>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupts = <2 1 0 0>; reg = <0x1>; }; phy4: ethernet-phy@4 { reg = <0x4>; }; tbi-phy@5 { device_type = "tbi-phy"; reg = <0x5>; }; }; mdio@25000 { tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; ethernet@b0000 { phy-handle = <&phy0>; phy-connection-type = "rgmii-id"; }; ethernet@b1000 { phy-handle = <&phy4>; tbi-handle = <&tbi0>; phy-connection-type = "sgmii"; }; ethernet@b2000 { phy-handle = <&phy1>; phy-connection-type = "rgmii-id"; }; par_io@e0100 { #address-cells = <1>; #size-cells = <1>; reg = <0xe0100 0x60>; ranges = <0x0 0xe0100 0x60>; device_type = "par_io"; num-ports = <3>; pio1: ucc_pin@1 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ }; pio2: ucc_pin@2 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ }; }; }; pci0: pcie@ffe09000 { reg = <0 0xffe09000 0 0x1000>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; pcie@0 { ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; pci1: pcie@ffe0a000 { reg = <0 0xffe0a000 0 0x1000>; ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; pcie@0 { ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; qe: qe@ffe80000 { ranges = <0x0 0x0 0xffe80000 0x40000>; reg = <0 0xffe80000 0 0x480>; brg-frequency = <0>; bus-frequency = <0>; status = "disabled"; /* no firmware loaded */ enet3: ucc@2000 { device_type = "network"; compatible = "ucc_geth"; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "clk12"; tx-clock-name = "clk9"; pio-handle = <&pio1>; phy-handle = <&qe_phy0>; phy-connection-type = "mii"; }; mdio@2120 { qe_phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <4 1 0 0>; reg = <0x0>; }; qe_phy1: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <5 1 0 0>; reg = <0x3>; }; tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet4: ucc@2400 { device_type = "network"; compatible = "ucc_geth"; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk13"; pio-handle = <&pio2>; phy-handle = <&qe_phy1>; phy-connection-type = "rmii"; }; }; }; /include/ "p1021si-post.dtsi" |