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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 | /* * ePAPR hcall interface * * Copyright 2008-2011 Freescale Semiconductor, Inc. * * Author: Timur Tabi <timur@freescale.com> * * This file is provided under a dual BSD/GPL license. When using or * redistributing this file, you may do so under either license. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* A "hypercall" is an "sc 1" instruction. This header file provides C * wrapper functions for the ePAPR hypervisor interface. It is inteded * for use by Linux device drivers and other operating systems. * * The hypercalls are implemented as inline assembly, rather than assembly * language functions in a .S file, for optimization. It allows * the caller to issue the hypercall instruction directly, improving both * performance and memory footprint. */ #ifndef _EPAPR_HCALLS_H #define _EPAPR_HCALLS_H #include <uapi/asm/epapr_hcalls.h> #ifndef __ASSEMBLY__ #include <linux/types.h> #include <linux/errno.h> #include <asm/byteorder.h> /* * Hypercall register clobber list * * These macros are used to define the list of clobbered registers during a * hypercall. Technically, registers r0 and r3-r12 are always clobbered, * but the gcc inline assembly syntax does not allow us to specify registers * on the clobber list that are also on the input/output list. Therefore, * the lists of clobbered registers depends on the number of register * parameters ("+r" and "=r") passed to the hypercall. * * Each assembly block should use one of the HCALL_CLOBBERSx macros. As a * general rule, 'x' is the number of parameters passed to the assembly * block *except* for r11. * * If you're not sure, just use the smallest value of 'x' that does not * generate a compilation error. Because these are static inline functions, * the compiler will only check the clobber list for a function if you * compile code that calls that function. * * r3 and r11 are not included in any clobbers list because they are always * listed as output registers. * * XER, CTR, and LR are currently listed as clobbers because it's uncertain * whether they will be clobbered. * * Note that r11 can be used as an output parameter. * * The "memory" clobber is only necessary for hcalls where the Hypervisor * will read or write guest memory. However, we add it to all hcalls because * the impact is minimal, and we want to ensure that it's present for the * hcalls that need it. */ /* List of common clobbered registers. Do not use this macro. */ #define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory" #define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS #define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10" #define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9" #define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8" #define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7" #define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6" #define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5" #define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4" extern bool epapr_paravirt_enabled; extern u32 epapr_hypercall_start[]; #ifdef CONFIG_EPAPR_PARAVIRT int __init epapr_paravirt_early_init(void); #else static inline int epapr_paravirt_early_init(void) { return 0; } #endif /* * We use "uintptr_t" to define a register because it's guaranteed to be a * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit * platform. * * All registers are either input/output or output only. Registers that are * initialized before making the hypercall are input/output. All * input/output registers are represented with "+r". Output-only registers * are represented with "=r". Do not specify any unused registers. The * clobber list will tell the compiler that the hypercall modifies those * registers, which is good enough. */ /** * ev_int_set_config - configure the specified interrupt * @interrupt: the interrupt number * @config: configuration for this interrupt * @priority: interrupt priority * @destination: destination CPU number * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_set_config(unsigned int interrupt, uint32_t config, unsigned int priority, uint32_t destination) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); register uintptr_t r5 __asm__("r5"); register uintptr_t r6 __asm__("r6"); r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG); r3 = interrupt; r4 = config; r5 = priority; r6 = destination; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6) : : EV_HCALL_CLOBBERS4 ); return r3; } /** * ev_int_get_config - return the config of the specified interrupt * @interrupt: the interrupt number * @config: returned configuration for this interrupt * @priority: returned interrupt priority * @destination: returned destination CPU number * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_get_config(unsigned int interrupt, uint32_t *config, unsigned int *priority, uint32_t *destination) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); register uintptr_t r5 __asm__("r5"); register uintptr_t r6 __asm__("r6"); r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG); r3 = interrupt; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6) : : EV_HCALL_CLOBBERS4 ); *config = r4; *priority = r5; *destination = r6; return r3; } /** * ev_int_set_mask - sets the mask for the specified interrupt source * @interrupt: the interrupt number * @mask: 0=enable interrupts, 1=disable interrupts * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_set_mask(unsigned int interrupt, unsigned int mask) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK); r3 = interrupt; r4 = mask; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "+r" (r4) : : EV_HCALL_CLOBBERS2 ); return r3; } /** * ev_int_get_mask - returns the mask for the specified interrupt source * @interrupt: the interrupt number * @mask: returned mask for this interrupt (0=enabled, 1=disabled) * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_get_mask(unsigned int interrupt, unsigned int *mask) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK); r3 = interrupt; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "=r" (r4) : : EV_HCALL_CLOBBERS2 ); *mask = r4; return r3; } /** * ev_int_eoi - signal the end of interrupt processing * @interrupt: the interrupt number * * This function signals the end of processing for the specified * interrupt, which must be the interrupt currently in service. By * definition, this is also the highest-priority interrupt. * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_eoi(unsigned int interrupt) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); r11 = EV_HCALL_TOKEN(EV_INT_EOI); r3 = interrupt; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3) : : EV_HCALL_CLOBBERS1 ); return r3; } /** * ev_byte_channel_send - send characters to a byte stream * @handle: byte stream handle * @count: (input) num of chars to send, (output) num chars sent * @buffer: pointer to a 16-byte buffer * * @buffer must be at least 16 bytes long, because all 16 bytes will be * read from memory into registers, even if count < 16. * * Returns 0 for success, or an error code. */ static inline unsigned int ev_byte_channel_send(unsigned int handle, unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); register uintptr_t r5 __asm__("r5"); register uintptr_t r6 __asm__("r6"); register uintptr_t r7 __asm__("r7"); register uintptr_t r8 __asm__("r8"); const uint32_t *p = (const uint32_t *) buffer; r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND); r3 = handle; r4 = *count; r5 = be32_to_cpu(p[0]); r6 = be32_to_cpu(p[1]); r7 = be32_to_cpu(p[2]); r8 = be32_to_cpu(p[3]); asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8) : : EV_HCALL_CLOBBERS6 ); *count = r4; return r3; } /** * ev_byte_channel_receive - fetch characters from a byte channel * @handle: byte channel handle * @count: (input) max num of chars to receive, (output) num chars received * @buffer: pointer to a 16-byte buffer * * The size of @buffer must be at least 16 bytes, even if you request fewer * than 16 characters, because we always write 16 bytes to @buffer. This is * for performance reasons. * * Returns 0 for success, or an error code. */ static inline unsigned int ev_byte_channel_receive(unsigned int handle, unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); register uintptr_t r5 __asm__("r5"); register uintptr_t r6 __asm__("r6"); register uintptr_t r7 __asm__("r7"); register uintptr_t r8 __asm__("r8"); uint32_t *p = (uint32_t *) buffer; r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE); r3 = handle; r4 = *count; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "+r" (r4), "=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8) : : EV_HCALL_CLOBBERS6 ); *count = r4; p[0] = cpu_to_be32(r5); p[1] = cpu_to_be32(r6); p[2] = cpu_to_be32(r7); p[3] = cpu_to_be32(r8); return r3; } /** * ev_byte_channel_poll - returns the status of the byte channel buffers * @handle: byte channel handle * @rx_count: returned count of bytes in receive queue * @tx_count: returned count of free space in transmit queue * * This function reports the amount of data in the receive queue (i.e. the * number of bytes you can read), and the amount of free space in the transmit * queue (i.e. the number of bytes you can write). * * Returns 0 for success, or an error code. */ static inline unsigned int ev_byte_channel_poll(unsigned int handle, unsigned int *rx_count, unsigned int *tx_count) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); register uintptr_t r5 __asm__("r5"); r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL); r3 = handle; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5) : : EV_HCALL_CLOBBERS3 ); *rx_count = r4; *tx_count = r5; return r3; } /** * ev_int_iack - acknowledge an interrupt * @handle: handle to the target interrupt controller * @vector: returned interrupt vector * * If handle is zero, the function returns the next interrupt source * number to be handled irrespective of the hierarchy or cascading * of interrupt controllers. If non-zero, specifies a handle to the * interrupt controller that is the target of the acknowledge. * * Returns 0 for success, or an error code. */ static inline unsigned int ev_int_iack(unsigned int handle, unsigned int *vector) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); register uintptr_t r4 __asm__("r4"); r11 = EV_HCALL_TOKEN(EV_INT_IACK); r3 = handle; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3), "=r" (r4) : : EV_HCALL_CLOBBERS2 ); *vector = r4; return r3; } /** * ev_doorbell_send - send a doorbell to another partition * @handle: doorbell send handle * * Returns 0 for success, or an error code. */ static inline unsigned int ev_doorbell_send(unsigned int handle) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND); r3 = handle; asm volatile("bl epapr_hypercall_start" : "+r" (r11), "+r" (r3) : : EV_HCALL_CLOBBERS1 ); return r3; } /** * ev_idle -- wait for next interrupt on this core * * Returns 0 for success, or an error code. */ static inline unsigned int ev_idle(void) { register uintptr_t r11 __asm__("r11"); register uintptr_t r3 __asm__("r3"); r11 = EV_HCALL_TOKEN(EV_IDLE); asm volatile("bl epapr_hypercall_start" : "+r" (r11), "=r" (r3) : : EV_HCALL_CLOBBERS1 ); return r3; } #ifdef CONFIG_EPAPR_PARAVIRT static inline unsigned long epapr_hypercall(unsigned long *in, unsigned long *out, unsigned long nr) { register unsigned long r0 asm("r0"); register unsigned long r3 asm("r3") = in[0]; register unsigned long r4 asm("r4") = in[1]; register unsigned long r5 asm("r5") = in[2]; register unsigned long r6 asm("r6") = in[3]; register unsigned long r7 asm("r7") = in[4]; register unsigned long r8 asm("r8") = in[5]; register unsigned long r9 asm("r9") = in[6]; register unsigned long r10 asm("r10") = in[7]; register unsigned long r11 asm("r11") = nr; register unsigned long r12 asm("r12"); asm volatile("bl epapr_hypercall_start" : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11), "=r"(r12) : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8), "r"(r9), "r"(r10), "r"(r11) : "memory", "cc", "xer", "ctr", "lr"); out[0] = r4; out[1] = r5; out[2] = r6; out[3] = r7; out[4] = r8; out[5] = r9; out[6] = r10; out[7] = r11; return r3; } #else static unsigned long epapr_hypercall(unsigned long *in, unsigned long *out, unsigned long nr) { return EV_UNIMPLEMENTED; } #endif static inline long epapr_hypercall0_1(unsigned int nr, unsigned long *r2) { unsigned long in[8] = {0}; unsigned long out[8]; unsigned long r; r = epapr_hypercall(in, out, nr); *r2 = out[0]; return r; } static inline long epapr_hypercall0(unsigned int nr) { unsigned long in[8] = {0}; unsigned long out[8]; return epapr_hypercall(in, out, nr); } static inline long epapr_hypercall1(unsigned int nr, unsigned long p1) { unsigned long in[8] = {0}; unsigned long out[8]; in[0] = p1; return epapr_hypercall(in, out, nr); } static inline long epapr_hypercall2(unsigned int nr, unsigned long p1, unsigned long p2) { unsigned long in[8] = {0}; unsigned long out[8]; in[0] = p1; in[1] = p2; return epapr_hypercall(in, out, nr); } static inline long epapr_hypercall3(unsigned int nr, unsigned long p1, unsigned long p2, unsigned long p3) { unsigned long in[8] = {0}; unsigned long out[8]; in[0] = p1; in[1] = p2; in[2] = p3; return epapr_hypercall(in, out, nr); } static inline long epapr_hypercall4(unsigned int nr, unsigned long p1, unsigned long p2, unsigned long p3, unsigned long p4) { unsigned long in[8] = {0}; unsigned long out[8]; in[0] = p1; in[1] = p2; in[2] = p3; in[3] = p4; return epapr_hypercall(in, out, nr); } #endif /* !__ASSEMBLY__ */ #endif /* _EPAPR_HCALLS_H */ |