Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 | // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. // Copyright (c) 2018, Linaro Limited #include <dt-bindings/sound/qcom,q6afe.h> #include <linux/err.h> #include <linux/init.h> #include <linux/module.h> #include <linux/device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <sound/pcm.h> #include <sound/soc.h> #include <sound/pcm_params.h> #include "q6dsp-lpass-ports.h" #include "q6dsp-common.h" #include "q6afe.h" struct q6afe_dai_priv_data { uint32_t sd_line_mask; uint32_t sync_mode; uint32_t sync_src; uint32_t data_out_enable; uint32_t invert_sync; uint32_t data_delay; uint32_t data_align; }; struct q6afe_dai_data { struct q6afe_port *port[AFE_PORT_MAX]; struct q6afe_port_config port_config[AFE_PORT_MAX]; bool is_port_started[AFE_PORT_MAX]; struct q6afe_dai_priv_data priv[AFE_PORT_MAX]; }; static int q6slim_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_slim_cfg *slim = &dai_data->port_config[dai->id].slim; slim->sample_rate = params_rate(params); switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_SPECIAL: slim->bit_width = 16; break; case SNDRV_PCM_FORMAT_S24_LE: slim->bit_width = 24; break; case SNDRV_PCM_FORMAT_S32_LE: slim->bit_width = 32; break; default: pr_err("%s: format %d\n", __func__, params_format(params)); return -EINVAL; } return 0; } static int q6hdmi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); int channels = params_channels(params); struct q6afe_hdmi_cfg *hdmi = &dai_data->port_config[dai->id].hdmi; int ret; hdmi->sample_rate = params_rate(params); switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: hdmi->bit_width = 16; break; case SNDRV_PCM_FORMAT_S24_LE: hdmi->bit_width = 24; break; } ret = q6dsp_get_channel_allocation(channels); if (ret < 0) return ret; hdmi->channel_allocation = (u16) ret; return 0; } static int q6i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_i2s_cfg *i2s = &dai_data->port_config[dai->id].i2s_cfg; i2s->sample_rate = params_rate(params); i2s->bit_width = params_width(params); i2s->num_channels = params_channels(params); i2s->sd_line_mask = dai_data->priv[dai->id].sd_line_mask; return 0; } static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_i2s_cfg *i2s = &dai_data->port_config[dai->id].i2s_cfg; i2s->fmt = fmt; return 0; } static int q6tdm_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm; unsigned int cap_mask; int rc = 0; /* HW only supports 16 and 32 bit slot width configuration */ if ((slot_width != 16) && (slot_width != 32)) { dev_err(dai->dev, "%s: invalid slot_width %d\n", __func__, slot_width); return -EINVAL; } /* HW supports 1-32 slots configuration. Typical: 1, 2, 4, 8, 16, 32 */ switch (slots) { case 2: cap_mask = 0x03; break; case 4: cap_mask = 0x0F; break; case 8: cap_mask = 0xFF; break; case 16: cap_mask = 0xFFFF; break; default: dev_err(dai->dev, "%s: invalid slots %d\n", __func__, slots); return -EINVAL; } switch (dai->id) { case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: tdm->nslots_per_frame = slots; tdm->slot_width = slot_width; /* TDM RX dais ids are even and tx are odd */ tdm->slot_mask = ((dai->id & 0x1) ? tx_mask : rx_mask) & cap_mask; break; default: dev_err(dai->dev, "%s: invalid dai id 0x%x\n", __func__, dai->id); return -EINVAL; } return rc; } static int q6tdm_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, unsigned int *tx_slot, unsigned int rx_num, unsigned int *rx_slot) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm; int rc = 0; int i = 0; switch (dai->id) { case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: if (dai->id & 0x1) { if (!tx_slot) { dev_err(dai->dev, "tx slot not found\n"); return -EINVAL; } if (tx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) { dev_err(dai->dev, "invalid tx num %d\n", tx_num); return -EINVAL; } for (i = 0; i < tx_num; i++) tdm->ch_mapping[i] = tx_slot[i]; for (i = tx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++) tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID; tdm->num_channels = tx_num; } else { /* rx */ if (!rx_slot) { dev_err(dai->dev, "rx slot not found\n"); return -EINVAL; } if (rx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) { dev_err(dai->dev, "invalid rx num %d\n", rx_num); return -EINVAL; } for (i = 0; i < rx_num; i++) tdm->ch_mapping[i] = rx_slot[i]; for (i = rx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++) tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID; tdm->num_channels = rx_num; } break; default: dev_err(dai->dev, "%s: invalid dai id 0x%x\n", __func__, dai->id); return -EINVAL; } return rc; } static int q6tdm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm; tdm->bit_width = params_width(params); tdm->sample_rate = params_rate(params); tdm->num_channels = params_channels(params); tdm->data_align_type = dai_data->priv[dai->id].data_align; tdm->sync_src = dai_data->priv[dai->id].sync_src; tdm->sync_mode = dai_data->priv[dai->id].sync_mode; return 0; } static int q6dma_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, unsigned int *tx_ch_mask, unsigned int rx_num, unsigned int *rx_ch_mask) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_cdc_dma_cfg *cfg = &dai_data->port_config[dai->id].dma_cfg; int ch_mask; int rc = 0; switch (dai->id) { case WSA_CODEC_DMA_TX_0: case WSA_CODEC_DMA_TX_1: case WSA_CODEC_DMA_TX_2: case VA_CODEC_DMA_TX_0: case VA_CODEC_DMA_TX_1: case VA_CODEC_DMA_TX_2: case TX_CODEC_DMA_TX_0: case TX_CODEC_DMA_TX_1: case TX_CODEC_DMA_TX_2: case TX_CODEC_DMA_TX_3: case TX_CODEC_DMA_TX_4: case TX_CODEC_DMA_TX_5: if (!tx_ch_mask) { dev_err(dai->dev, "tx slot not found\n"); return -EINVAL; } if (tx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) { dev_err(dai->dev, "invalid tx num %d\n", tx_num); return -EINVAL; } ch_mask = *tx_ch_mask; break; case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_2: case RX_CODEC_DMA_RX_3: case RX_CODEC_DMA_RX_4: case RX_CODEC_DMA_RX_5: case RX_CODEC_DMA_RX_6: case RX_CODEC_DMA_RX_7: /* rx */ if (!rx_ch_mask) { dev_err(dai->dev, "rx slot not found\n"); return -EINVAL; } if (rx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) { dev_err(dai->dev, "invalid rx num %d\n", rx_num); return -EINVAL; } ch_mask = *rx_ch_mask; break; default: dev_err(dai->dev, "%s: invalid dai id 0x%x\n", __func__, dai->id); return -EINVAL; } cfg->active_channels_mask = ch_mask; return rc; } static int q6dma_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_cdc_dma_cfg *cfg = &dai_data->port_config[dai->id].dma_cfg; cfg->bit_width = params_width(params); cfg->sample_rate = params_rate(params); cfg->num_channels = params_channels(params); return 0; } static void q6afe_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); int rc; if (!dai_data->is_port_started[dai->id]) return; rc = q6afe_port_stop(dai_data->port[dai->id]); if (rc < 0) dev_err(dai->dev, "fail to close AFE port (%d)\n", rc); dai_data->is_port_started[dai->id] = false; } static int q6afe_dai_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); int rc; if (dai_data->is_port_started[dai->id]) { /* stop the port and restart with new port config */ rc = q6afe_port_stop(dai_data->port[dai->id]); if (rc < 0) { dev_err(dai->dev, "fail to close AFE port (%d)\n", rc); return rc; } } switch (dai->id) { case HDMI_RX: case DISPLAY_PORT_RX: q6afe_hdmi_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].hdmi); break; case SLIMBUS_0_RX ... SLIMBUS_6_TX: q6afe_slim_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].slim); break; case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: rc = q6afe_i2s_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].i2s_cfg); if (rc < 0) { dev_err(dai->dev, "fail to prepare AFE port %x\n", dai->id); return rc; } break; case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: q6afe_tdm_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].tdm); break; case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7: q6afe_cdc_dma_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].dma_cfg); break; default: return -EINVAL; } rc = q6afe_port_start(dai_data->port[dai->id]); if (rc < 0) { dev_err(dai->dev, "fail to start AFE port %x\n", dai->id); return rc; } dai_data->is_port_started[dai->id] = true; return 0; } static int q6slim_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, unsigned int *tx_slot, unsigned int rx_num, unsigned int *rx_slot) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_port_config *pcfg = &dai_data->port_config[dai->id]; int i; if (dai->id & 0x1) { /* TX */ if (!tx_slot) { pr_err("%s: tx slot not found\n", __func__); return -EINVAL; } for (i = 0; i < tx_num; i++) pcfg->slim.ch_mapping[i] = tx_slot[i]; pcfg->slim.num_channels = tx_num; } else { if (!rx_slot) { pr_err("%s: rx slot not found\n", __func__); return -EINVAL; } for (i = 0; i < rx_num; i++) pcfg->slim.ch_mapping[i] = rx_slot[i]; pcfg->slim.num_channels = rx_num; } return 0; } static int q6afe_mi2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_port *port = dai_data->port[dai->id]; switch (clk_id) { case LPAIF_DIG_CLK: return q6afe_port_set_sysclk(port, clk_id, 0, 5, freq, dir); case LPAIF_BIT_CLK: case LPAIF_OSR_CLK: return q6afe_port_set_sysclk(port, clk_id, Q6AFE_LPASS_CLK_SRC_INTERNAL, Q6AFE_LPASS_CLK_ROOT_DEFAULT, freq, dir); case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: return q6afe_port_set_sysclk(port, clk_id, Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, Q6AFE_LPASS_CLK_ROOT_DEFAULT, freq, dir); case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: return q6afe_port_set_sysclk(port, clk_id, Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO, Q6AFE_LPASS_CLK_ROOT_DEFAULT, freq, dir); } return 0; } static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { {"HDMI Playback", NULL, "HDMI_RX"}, {"DISPLAY_PORT_RX_0 Playback", NULL, "DISPLAY_PORT_RX"}, {"Slimbus Playback", NULL, "SLIMBUS_0_RX"}, {"Slimbus1 Playback", NULL, "SLIMBUS_1_RX"}, {"Slimbus2 Playback", NULL, "SLIMBUS_2_RX"}, {"Slimbus3 Playback", NULL, "SLIMBUS_3_RX"}, {"Slimbus4 Playback", NULL, "SLIMBUS_4_RX"}, {"Slimbus5 Playback", NULL, "SLIMBUS_5_RX"}, {"Slimbus6 Playback", NULL, "SLIMBUS_6_RX"}, {"SLIMBUS_0_TX", NULL, "Slimbus Capture"}, {"SLIMBUS_1_TX", NULL, "Slimbus1 Capture"}, {"SLIMBUS_2_TX", NULL, "Slimbus2 Capture"}, {"SLIMBUS_3_TX", NULL, "Slimbus3 Capture"}, {"SLIMBUS_4_TX", NULL, "Slimbus4 Capture"}, {"SLIMBUS_5_TX", NULL, "Slimbus5 Capture"}, {"SLIMBUS_6_TX", NULL, "Slimbus6 Capture"}, {"Primary MI2S Playback", NULL, "PRI_MI2S_RX"}, {"Secondary MI2S Playback", NULL, "SEC_MI2S_RX"}, {"Tertiary MI2S Playback", NULL, "TERT_MI2S_RX"}, {"Quaternary MI2S Playback", NULL, "QUAT_MI2S_RX"}, {"Quinary MI2S Playback", NULL, "QUIN_MI2S_RX"}, {"Primary TDM0 Playback", NULL, "PRIMARY_TDM_RX_0"}, {"Primary TDM1 Playback", NULL, "PRIMARY_TDM_RX_1"}, {"Primary TDM2 Playback", NULL, "PRIMARY_TDM_RX_2"}, {"Primary TDM3 Playback", NULL, "PRIMARY_TDM_RX_3"}, {"Primary TDM4 Playback", NULL, "PRIMARY_TDM_RX_4"}, {"Primary TDM5 Playback", NULL, "PRIMARY_TDM_RX_5"}, {"Primary TDM6 Playback", NULL, "PRIMARY_TDM_RX_6"}, {"Primary TDM7 Playback", NULL, "PRIMARY_TDM_RX_7"}, {"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"}, {"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"}, {"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"}, {"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"}, {"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"}, {"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"}, {"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"}, {"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"}, {"Tertiary TDM0 Playback", NULL, "TERT_TDM_RX_0"}, {"Tertiary TDM1 Playback", NULL, "TERT_TDM_RX_1"}, {"Tertiary TDM2 Playback", NULL, "TERT_TDM_RX_2"}, {"Tertiary TDM3 Playback", NULL, "TERT_TDM_RX_3"}, {"Tertiary TDM4 Playback", NULL, "TERT_TDM_RX_4"}, {"Tertiary TDM5 Playback", NULL, "TERT_TDM_RX_5"}, {"Tertiary TDM6 Playback", NULL, "TERT_TDM_RX_6"}, {"Tertiary TDM7 Playback", NULL, "TERT_TDM_RX_7"}, {"Quaternary TDM0 Playback", NULL, "QUAT_TDM_RX_0"}, {"Quaternary TDM1 Playback", NULL, "QUAT_TDM_RX_1"}, {"Quaternary TDM2 Playback", NULL, "QUAT_TDM_RX_2"}, {"Quaternary TDM3 Playback", NULL, "QUAT_TDM_RX_3"}, {"Quaternary TDM4 Playback", NULL, "QUAT_TDM_RX_4"}, {"Quaternary TDM5 Playback", NULL, "QUAT_TDM_RX_5"}, {"Quaternary TDM6 Playback", NULL, "QUAT_TDM_RX_6"}, {"Quaternary TDM7 Playback", NULL, "QUAT_TDM_RX_7"}, {"Quinary TDM0 Playback", NULL, "QUIN_TDM_RX_0"}, {"Quinary TDM1 Playback", NULL, "QUIN_TDM_RX_1"}, {"Quinary TDM2 Playback", NULL, "QUIN_TDM_RX_2"}, {"Quinary TDM3 Playback", NULL, "QUIN_TDM_RX_3"}, {"Quinary TDM4 Playback", NULL, "QUIN_TDM_RX_4"}, {"Quinary TDM5 Playback", NULL, "QUIN_TDM_RX_5"}, {"Quinary TDM6 Playback", NULL, "QUIN_TDM_RX_6"}, {"Quinary TDM7 Playback", NULL, "QUIN_TDM_RX_7"}, {"PRIMARY_TDM_TX_0", NULL, "Primary TDM0 Capture"}, {"PRIMARY_TDM_TX_1", NULL, "Primary TDM1 Capture"}, {"PRIMARY_TDM_TX_2", NULL, "Primary TDM2 Capture"}, {"PRIMARY_TDM_TX_3", NULL, "Primary TDM3 Capture"}, {"PRIMARY_TDM_TX_4", NULL, "Primary TDM4 Capture"}, {"PRIMARY_TDM_TX_5", NULL, "Primary TDM5 Capture"}, {"PRIMARY_TDM_TX_6", NULL, "Primary TDM6 Capture"}, {"PRIMARY_TDM_TX_7", NULL, "Primary TDM7 Capture"}, {"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"}, {"SEC_TDM_TX_1", NULL, "Secondary TDM1 Capture"}, {"SEC_TDM_TX_2", NULL, "Secondary TDM2 Capture"}, {"SEC_TDM_TX_3", NULL, "Secondary TDM3 Capture"}, {"SEC_TDM_TX_4", NULL, "Secondary TDM4 Capture"}, {"SEC_TDM_TX_5", NULL, "Secondary TDM5 Capture"}, {"SEC_TDM_TX_6", NULL, "Secondary TDM6 Capture"}, {"SEC_TDM_TX_7", NULL, "Secondary TDM7 Capture"}, {"TERT_TDM_TX_0", NULL, "Tertiary TDM0 Capture"}, {"TERT_TDM_TX_1", NULL, "Tertiary TDM1 Capture"}, {"TERT_TDM_TX_2", NULL, "Tertiary TDM2 Capture"}, {"TERT_TDM_TX_3", NULL, "Tertiary TDM3 Capture"}, {"TERT_TDM_TX_4", NULL, "Tertiary TDM4 Capture"}, {"TERT_TDM_TX_5", NULL, "Tertiary TDM5 Capture"}, {"TERT_TDM_TX_6", NULL, "Tertiary TDM6 Capture"}, {"TERT_TDM_TX_7", NULL, "Tertiary TDM7 Capture"}, {"QUAT_TDM_TX_0", NULL, "Quaternary TDM0 Capture"}, {"QUAT_TDM_TX_1", NULL, "Quaternary TDM1 Capture"}, {"QUAT_TDM_TX_2", NULL, "Quaternary TDM2 Capture"}, {"QUAT_TDM_TX_3", NULL, "Quaternary TDM3 Capture"}, {"QUAT_TDM_TX_4", NULL, "Quaternary TDM4 Capture"}, {"QUAT_TDM_TX_5", NULL, "Quaternary TDM5 Capture"}, {"QUAT_TDM_TX_6", NULL, "Quaternary TDM6 Capture"}, {"QUAT_TDM_TX_7", NULL, "Quaternary TDM7 Capture"}, {"QUIN_TDM_TX_0", NULL, "Quinary TDM0 Capture"}, {"QUIN_TDM_TX_1", NULL, "Quinary TDM1 Capture"}, {"QUIN_TDM_TX_2", NULL, "Quinary TDM2 Capture"}, {"QUIN_TDM_TX_3", NULL, "Quinary TDM3 Capture"}, {"QUIN_TDM_TX_4", NULL, "Quinary TDM4 Capture"}, {"QUIN_TDM_TX_5", NULL, "Quinary TDM5 Capture"}, {"QUIN_TDM_TX_6", NULL, "Quinary TDM6 Capture"}, {"QUIN_TDM_TX_7", NULL, "Quinary TDM7 Capture"}, {"TERT_MI2S_TX", NULL, "Tertiary MI2S Capture"}, {"PRI_MI2S_TX", NULL, "Primary MI2S Capture"}, {"SEC_MI2S_TX", NULL, "Secondary MI2S Capture"}, {"QUAT_MI2S_TX", NULL, "Quaternary MI2S Capture"}, {"QUIN_MI2S_TX", NULL, "Quinary MI2S Capture"}, {"WSA_CODEC_DMA_RX_0 Playback", NULL, "WSA_CODEC_DMA_RX_0"}, {"WSA_CODEC_DMA_TX_0", NULL, "WSA_CODEC_DMA_TX_0 Capture"}, {"WSA_CODEC_DMA_RX_1 Playback", NULL, "WSA_CODEC_DMA_RX_1"}, {"WSA_CODEC_DMA_TX_1", NULL, "WSA_CODEC_DMA_TX_1 Capture"}, {"WSA_CODEC_DMA_TX_2", NULL, "WSA_CODEC_DMA_TX_2 Capture"}, {"VA_CODEC_DMA_TX_0", NULL, "VA_CODEC_DMA_TX_0 Capture"}, {"VA_CODEC_DMA_TX_1", NULL, "VA_CODEC_DMA_TX_1 Capture"}, {"VA_CODEC_DMA_TX_2", NULL, "VA_CODEC_DMA_TX_2 Capture"}, {"RX_CODEC_DMA_RX_0 Playback", NULL, "RX_CODEC_DMA_RX_0"}, {"TX_CODEC_DMA_TX_0", NULL, "TX_CODEC_DMA_TX_0 Capture"}, {"RX_CODEC_DMA_RX_1 Playback", NULL, "RX_CODEC_DMA_RX_1"}, {"TX_CODEC_DMA_TX_1", NULL, "TX_CODEC_DMA_TX_1 Capture"}, {"RX_CODEC_DMA_RX_2 Playback", NULL, "RX_CODEC_DMA_RX_2"}, {"TX_CODEC_DMA_TX_2", NULL, "TX_CODEC_DMA_TX_2 Capture"}, {"RX_CODEC_DMA_RX_3 Playback", NULL, "RX_CODEC_DMA_RX_3"}, {"TX_CODEC_DMA_TX_3", NULL, "TX_CODEC_DMA_TX_3 Capture"}, {"RX_CODEC_DMA_RX_4 Playback", NULL, "RX_CODEC_DMA_RX_4"}, {"TX_CODEC_DMA_TX_4", NULL, "TX_CODEC_DMA_TX_4 Capture"}, {"RX_CODEC_DMA_RX_5 Playback", NULL, "RX_CODEC_DMA_RX_5"}, {"TX_CODEC_DMA_TX_5", NULL, "TX_CODEC_DMA_TX_5 Capture"}, {"RX_CODEC_DMA_RX_6 Playback", NULL, "RX_CODEC_DMA_RX_6"}, {"RX_CODEC_DMA_RX_7 Playback", NULL, "RX_CODEC_DMA_RX_7"}, }; static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); struct q6afe_port *port; port = q6afe_port_get_from_id(dai->dev, dai->id); if (IS_ERR(port)) { dev_err(dai->dev, "Unable to get afe port\n"); return -EINVAL; } dai_data->port[dai->id] = port; return 0; } static int msm_dai_q6_dai_remove(struct snd_soc_dai *dai) { struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev); q6afe_port_put(dai_data->port[dai->id]); dai_data->port[dai->id] = NULL; return 0; } static const struct snd_soc_dai_ops q6hdmi_ops = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, .prepare = q6afe_dai_prepare, .hw_params = q6hdmi_hw_params, .shutdown = q6afe_dai_shutdown, }; static const struct snd_soc_dai_ops q6i2s_ops = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, .prepare = q6afe_dai_prepare, .hw_params = q6i2s_hw_params, .set_fmt = q6i2s_set_fmt, .shutdown = q6afe_dai_shutdown, .set_sysclk = q6afe_mi2s_set_sysclk, }; static const struct snd_soc_dai_ops q6slim_ops = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, .prepare = q6afe_dai_prepare, .hw_params = q6slim_hw_params, .shutdown = q6afe_dai_shutdown, .set_channel_map = q6slim_set_channel_map, }; static const struct snd_soc_dai_ops q6tdm_ops = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, .prepare = q6afe_dai_prepare, .shutdown = q6afe_dai_shutdown, .set_sysclk = q6afe_mi2s_set_sysclk, .set_tdm_slot = q6tdm_set_tdm_slot, .set_channel_map = q6tdm_set_channel_map, .hw_params = q6tdm_hw_params, }; static const struct snd_soc_dai_ops q6dma_ops = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, .prepare = q6afe_dai_prepare, .shutdown = q6afe_dai_shutdown, .set_sysclk = q6afe_mi2s_set_sysclk, .set_channel_map = q6dma_set_channel_map, .hw_params = q6dma_hw_params, }; static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = { SND_SOC_DAPM_AIF_IN("HDMI_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_0_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_1_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_2_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_3_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_4_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_5_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_6_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_0_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_1_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_2_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_3_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_5_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIMBUS_6_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_MI2S_RX_SD1", "Secondary MI2S Playback SD1", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRI_MI2S_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRI_MI2S_TX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_0", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_1", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_2", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_3", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_4", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_5", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_6", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_7", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT_RX", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("WSA_CODEC_DMA_RX_0", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_0", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("WSA_CODEC_DMA_RX_1", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_1", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_2", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_0", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_1", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_2", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_0", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_0", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_1", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_1", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_2", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_2", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_3", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_3", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_4", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_4", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_5", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_5", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_6", "NULL", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_7", "NULL", 0, SND_SOC_NOPM, 0, 0), }; static const struct snd_soc_component_driver q6afe_dai_component = { .name = "q6afe-dai-component", .dapm_widgets = q6afe_dai_widgets, .num_dapm_widgets = ARRAY_SIZE(q6afe_dai_widgets), .dapm_routes = q6afe_dapm_routes, .num_dapm_routes = ARRAY_SIZE(q6afe_dapm_routes), .of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name, }; static void of_q6afe_parse_dai_data(struct device *dev, struct q6afe_dai_data *data) { struct device_node *node; int ret; for_each_child_of_node(dev->of_node, node) { unsigned int lines[Q6AFE_MAX_MI2S_LINES]; struct q6afe_dai_priv_data *priv; int id, i, num_lines; ret = of_property_read_u32(node, "reg", &id); if (ret || id < 0 || id >= AFE_PORT_MAX) { dev_err(dev, "valid dai id not found:%d\n", ret); continue; } switch (id) { /* MI2S specific properties */ case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: priv = &data->priv[id]; ret = of_property_read_variable_u32_array(node, "qcom,sd-lines", lines, 0, Q6AFE_MAX_MI2S_LINES); if (ret < 0) num_lines = 0; else num_lines = ret; priv->sd_line_mask = 0; for (i = 0; i < num_lines; i++) priv->sd_line_mask |= BIT(lines[i]); break; case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: priv = &data->priv[id]; ret = of_property_read_u32(node, "qcom,tdm-sync-mode", &priv->sync_mode); if (ret) { dev_err(dev, "No Sync mode from DT\n"); break; } ret = of_property_read_u32(node, "qcom,tdm-sync-src", &priv->sync_src); if (ret) { dev_err(dev, "No Sync Src from DT\n"); break; } ret = of_property_read_u32(node, "qcom,tdm-data-out", &priv->data_out_enable); if (ret) { dev_err(dev, "No Data out enable from DT\n"); break; } ret = of_property_read_u32(node, "qcom,tdm-invert-sync", &priv->invert_sync); if (ret) { dev_err(dev, "No Invert sync from DT\n"); break; } ret = of_property_read_u32(node, "qcom,tdm-data-delay", &priv->data_delay); if (ret) { dev_err(dev, "No Data Delay from DT\n"); break; } ret = of_property_read_u32(node, "qcom,tdm-data-align", &priv->data_align); if (ret) { dev_err(dev, "No Data align from DT\n"); break; } break; default: break; } } } static int q6afe_dai_dev_probe(struct platform_device *pdev) { struct q6dsp_audio_port_dai_driver_config cfg; struct snd_soc_dai_driver *dais; struct q6afe_dai_data *dai_data; struct device *dev = &pdev->dev; int num_dais; dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL); if (!dai_data) return -ENOMEM; dev_set_drvdata(dev, dai_data); of_q6afe_parse_dai_data(dev, dai_data); cfg.q6hdmi_ops = &q6hdmi_ops; cfg.q6slim_ops = &q6slim_ops; cfg.q6i2s_ops = &q6i2s_ops; cfg.q6tdm_ops = &q6tdm_ops; cfg.q6dma_ops = &q6dma_ops; dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais); return devm_snd_soc_register_component(dev, &q6afe_dai_component, dais, num_dais); } #ifdef CONFIG_OF static const struct of_device_id q6afe_dai_device_id[] = { { .compatible = "qcom,q6afe-dais" }, {}, }; MODULE_DEVICE_TABLE(of, q6afe_dai_device_id); #endif static struct platform_driver q6afe_dai_platform_driver = { .driver = { .name = "q6afe-dai", .of_match_table = of_match_ptr(q6afe_dai_device_id), }, .probe = q6afe_dai_dev_probe, }; module_platform_driver(q6afe_dai_platform_driver); MODULE_DESCRIPTION("Q6 Audio Frontend dai driver"); MODULE_LICENSE("GPL v2"); |