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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * SNI specific PCI support for RM200/RM300. * * Copyright (C) 1997 - 2000, 2003 Ralf Baechle <ralf@linux-mips.org> */ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/types.h> #include <asm/sni.h> /* * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device * address are decoded. We therefore manually have to reject attempts at * reading outside this range. Being on the paranoid side we only do this * test for bus 0 and hope forwarding and decoding work properly for any * subordinated busses. * * ASIC PCI only supports type 1 config cycles. */ static int set_config_address(unsigned int busno, unsigned int devfn, int reg) { if ((devfn > 255) || (reg > 255)) return PCIBIOS_BAD_REGISTER_NUMBER; if (busno == 0 && devfn >= PCI_DEVFN(8, 0)) return PCIBIOS_DEVICE_NOT_FOUND; *(volatile u32 *)PCIMT_CONFIG_ADDRESS = ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc); return PCIBIOS_SUCCESSFUL; } static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 * val) { int res; if ((res = set_config_address(bus->number, devfn, reg))) return res; switch (size) { case 1: *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: *val = inl(PCIMT_CONFIG_DATA); break; } return 0; } static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) { int res; if ((res = set_config_address(bus->number, devfn, reg))) return res; switch (size) { case 1: outb(val, PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: outw(val, PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: outl(val, PCIMT_CONFIG_DATA); break; } return 0; } struct pci_ops sni_pcimt_ops = { .read = pcimt_read, .write = pcimt_write, }; static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg) { if ((devfn > 255) || (reg > 255) || (busno > 255)) return PCIBIOS_BAD_REGISTER_NUMBER; outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); return PCIBIOS_SUCCESSFUL; } static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 * val) { int res; /* * on bus 0 we need to check, whether there is a device answering * for the devfn by doing a config write and checking the result. If * we don't do it, we will get a data bus error */ if (bus->number == 0) { pcit_set_config_address(0, 0, 0x68); outl(inl(0xcfc) | 0xc0000000, 0xcfc); if ((res = pcit_set_config_address(0, devfn, 0))) return res; outl(0xffffffff, 0xcfc); pcit_set_config_address(0, 0, 0x68); if (inl(0xcfc) & 0x100000) return PCIBIOS_DEVICE_NOT_FOUND; } if ((res = pcit_set_config_address(bus->number, devfn, reg))) return res; switch (size) { case 1: *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: *val = inl(PCIMT_CONFIG_DATA); break; } return 0; } static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) { int res; if ((res = pcit_set_config_address(bus->number, devfn, reg))) return res; switch (size) { case 1: outb(val, PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: outw(val, PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: outl(val, PCIMT_CONFIG_DATA); break; } return 0; } struct pci_ops sni_pcit_ops = { .read = pcit_read, .write = pcit_write, }; |