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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2018 Boundary Devices * Copyright 2021 Lucas Stach <dev@lynxeye.de> */ #include "imx8mq.dtsi" / { model = "Boundary Devices i.MX8MQ Nitrogen8M"; compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; chosen { stdout-path = &uart1; }; reg_1p8v: regulator-fixed-1v8 { compatible = "regulator-fixed"; regulator-name = "1P8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; reg_snvs: regulator-fixed-snvs { compatible = "regulator-fixed"; regulator-name = "VDD_SNVS"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; }; &{/opp-table/opp-800000000} { opp-microvolt = <1000000>; }; &{/opp-table/opp-1000000000} { opp-microvolt = <1000000>; }; &A53_0 { cpu-supply = <®_arm_dram>; }; &A53_1 { cpu-supply = <®_arm_dram>; }; &A53_2 { cpu-supply = <®_arm_dram>; }; &A53_3 { cpu-supply = <®_arm_dram>; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <300>; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; i2c-mux@70 { compatible = "nxp,pca9546"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_pca9546>; reg = <0x70>; reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; i2c1a: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; reg_arm_dram: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; regulator-name = "VDD_ARM_DRAM_1V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; }; i2c1b: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; reg_dram_1p1v: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; regulator-name = "NVCC_DRAM_1P1V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; }; i2c1c: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; reg_soc_gpu_vpu: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; regulator-name = "VDD_SOC_GPU_VPU"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-always-on; }; }; i2c1d: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; }; }; }; &pgc_gpu { power-supply = <®_soc_gpu_vpu>; }; &pgc_vpu { power-supply = <®_soc_gpu_vpu>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usdhc1 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; vqmmc-supply = <®_1p8v>; vmmc-supply = <®_snvs>; bus-width = <8>; non-removable; no-mmc-hs400; no-sdio; no-sd; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 >; }; pinctrl_i2c1_pca9546: i2c1-pca9546grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; }; |