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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 | // SPDX-License-Identifier: GPL-2.0 #include "tegra20.dtsi" /* * Toradex Colibri T20 Module Device Tree * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; * Colibri T20 512MB IT V1.2A */ / { memory@0 { /* * Set memory to 256 MB to be safe as this could be used on * 256 or 512 MB module. It is expected from bootloader * to fix this up for 512 MB version. */ reg = <0x00000000 0x10000000>; }; host1x@50000000 { hdmi@54280000 { nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; pll-supply = <®_1v8_avdd_hdmi_pll>; vdd-supply = <®_3v3_avdd_hdmi>; }; }; gpio@6000d000 { lan-reset-n-hog { gpio-hog; gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>; output-high; line-name = "LAN_RESET#"; }; /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ npwe-hog { gpio-hog; gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; output-high; line-name = "Tri-state nPWE"; }; /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ rdnwr-hog { gpio-hog; gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; output-low; line-name = "Not tri-state RDnWR"; }; }; pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; state_default: pinmux { /* Analogue Audio AC97 to WM9712 (On-module) */ audio-refclk { nvidia,pins = "cdev1"; nvidia,function = "plla_out"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; dap3 { nvidia,pins = "dap3"; nvidia,function = "dap3"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ * (All on-module), SODIMM Pin 45 Wakeup */ gpio-uac { nvidia,pins = "uac"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * Buffer Enables for nPWE and RDnWR (On-module, * see GPIO hogging further down below) */ gpio-pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, * SYS_CLK_REQ (All on-module) */ pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * Colibri Address/Data Bus (GMI) * Note: spid and spie optionally used for SPI1 */ gmi { nvidia,pins = "atc", "atd", "ate", "dap1", "dap2", "dap4", "gmd", "gpu", "irrx", "irtx", "spia", "spib", "spic", "spid", "spie", "uca", "ucb"; nvidia,function = "gmi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Further pins may be used as GPIOs */ gmi-gpio1 { nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; nvidia,function = "hdmi"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; gmi-gpio2 { nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; nvidia,function = "rsvd4"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri BL_ON */ bl-on { nvidia,pins = "dta"; nvidia,function = "rsvd1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri Backlight PWM<A>, PWM<B> */ sdc { nvidia,pins = "sdc"; nvidia,function = "pwm"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri DDC */ ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * Colibri EXT_IO* * Note: dtf optionally used for I2C3 */ ext-io { nvidia,pins = "dtf", "spdi"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * Colibri Ethernet (On-module) * ULPI EHCI instance 1 USB2_DP/N -> AX88772B */ ulpi { nvidia,pins = "uaa", "uab", "uda"; nvidia,function = "ulpi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; ulpi-refclk { nvidia,pins = "cdev2"; nvidia,function = "pllp_out4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* Colibri HOTPLUG_DETECT (HDMI) */ hotplug-detect { nvidia,pins = "hdint"; nvidia,function = "hdmi"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri I2C */ i2c { nvidia,pins = "rm"; nvidia,function = "i2c1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE * today's display need DE, disable LCD_M1 */ lm1 { nvidia,pins = "lm1"; nvidia,function = "rsvd3"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri LCD (L_* resp. LDD<*>) */ lcd { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", "ld5", "ld6", "ld7", "ld8", "ld9", "ld10", "ld11", "ld12", "ld13", "ld14", "ld15", "ld16", "ld17", "lhs", "lsc0", "lspi", "lvs"; nvidia,function = "displaya"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri LCD (Optional 24 BPP Support) */ lcd-24 { nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", "lpp", "lvp1"; nvidia,function = "displaya"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri MMC */ mmc { nvidia,pins = "atb", "gma"; nvidia,function = "sdio4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri MMCCD */ mmccd { nvidia,pins = "gmb"; nvidia,function = "gmi_int"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri MMC (Optional 8-bit) */ mmc-8bit { nvidia,pins = "gme"; nvidia,function = "sdio4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * Colibri Parallel Camera (Optional) * pins multiplexed with others and therefore disabled * Note: dta used for BL_ON by default */ cif-mclk { nvidia,pins = "csus"; nvidia,function = "vi_sensor_clk"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; cif { nvidia,pins = "dtb", "dtc", "dtd"; nvidia,function = "vi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri PWM<C>, PWM<D> */ sdb_sdd { nvidia,pins = "sdb", "sdd"; nvidia,function = "pwm"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri SSP */ ssp { nvidia,pins = "slxa", "slxc", "slxd", "slxk"; nvidia,function = "spi4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri UART-A */ uart-a { nvidia,pins = "sdio1"; nvidia,function = "uarta"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; uart-a-dsr { nvidia,pins = "lpw1"; nvidia,function = "rsvd3"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; uart-a-dcd { nvidia,pins = "lpw2"; nvidia,function = "hdmi"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri UART-B */ uart-b { nvidia,pins = "gmc"; nvidia,function = "uartd"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri UART-C */ uart-c { nvidia,pins = "uad"; nvidia,function = "irda"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri USB_CDET */ usb-cdet { nvidia,pins = "spdo"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri USBH_OC */ usbh-oc { nvidia,pins = "spih"; nvidia,function = "spi2_alt"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri USBH_PEN */ usbh-pen { nvidia,pins = "spig"; nvidia,function = "spi2_alt"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Colibri VGA not supported */ vga { nvidia,pins = "crtp"; nvidia,function = "crt"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* I2C3 (Optional) */ i2c3 { nvidia,pins = "dtf"; nvidia,function = "i2c3"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* JTAG_RTCK */ jtag-rtck { nvidia,pins = "gpu7"; nvidia,function = "rtck"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME * (All On-module) */ gpio-gpv { nvidia,pins = "gpv"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN * (All On-module); Colibri CAN_INT */ gpio-dte { nvidia,pins = "dte"; nvidia,function = "rsvd1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* NAND (On-module) */ nand { nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf"; nvidia,function = "nand"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* Onewire (Optional) */ owr { nvidia,pins = "owc"; nvidia,function = "owr"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* Power I2C (On-module) */ i2cp { nvidia,pins = "i2cp"; nvidia,function = "i2cp"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* RESET_OUT */ reset-out { nvidia,pins = "ata"; nvidia,function = "gmi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; /* * SPI1 (Optional) * Note: spid and spie used for Colibri Address/Data * Bus (GMI) */ spi1 { nvidia,pins = "spid", "spie", "spif"; nvidia,function = "spi1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; /* * THERMD_ALERT# (On-module), unlatched I2C address pin * of LM95245 temperature sensor therefore requires * disabling for now */ lvp0 { nvidia,pins = "lvp0"; nvidia,function = "rsvd3"; nvidia,tristate = <TEGRA_PIN_ENABLE>; }; }; }; tegra_ac97: ac97@70002000 { status = "okay"; nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; }; serial@70006040 { compatible = "nvidia,tegra20-hsuart"; reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra20-hsuart"; reset-names = "serial"; /delete-property/ reg-shift; }; nand-controller@70008000 { status = "okay"; nand@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; nand-bus-width = <8>; nand-on-flash-bbt; nand-ecc-algo = "bch"; nand-is-boot-medium; nand-ecc-maximize; wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; }; }; /* * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier * board) */ i2c@7000c000 { clock-frequency = <400000>; }; /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ hdmi_ddc: i2c@7000c400 { clock-frequency = <10000>; }; /* GEN2_I2C: unused */ /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ i2c@7000d000 { status = "okay"; clock-frequency = <100000>; pmic@34 { compatible = "ti,tps6586x"; reg = <0x34>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ti,system-power-controller; #gpio-cells = <2>; gpio-controller; sys-supply = <®_module_3v3>; vin-sm0-supply = <®_3v3_vsys>; vin-sm1-supply = <®_3v3_vsys>; vin-sm2-supply = <®_3v3_vsys>; vinldo01-supply = <®_1v8_vdd_ddr2>; vinldo23-supply = <®_module_3v3>; vinldo4-supply = <®_module_3v3>; vinldo678-supply = <®_module_3v3>; vinldo9-supply = <®_module_3v3>; regulators { reg_3v3_vsys: sys { regulator-name = "VSYS_3.3V"; regulator-always-on; }; vdd_core: sm0 { regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; sm1 { regulator-name = "VDD_CPU_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; reg_1v8_vdd_ddr2: sm2 { regulator-name = "VDD_DDR2_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; /* LDO0 is not connected to anything */ /* * +3.3V_ENABLE_N switching via FET: * AVDD_AUDIO_S and +3.3V * see also +3.3V fixed supply */ ldo1 { regulator-name = "AVDD_PLL_1.1V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; ldo2 { regulator-name = "VDD_RTC_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; /* LDO3 is not connected to anything */ ldo4 { regulator-name = "VDDIO_SYS_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; /* Switched via FET from regular +3.3V */ ldo5 { regulator-name = "+3.3V_USB"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; ldo6 { regulator-name = "AVDD_VDAC_2.85V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; }; reg_3v3_avdd_hdmi: ldo7 { regulator-name = "AVDD_HDMI_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; reg_1v8_avdd_hdmi_pll: ldo8 { regulator-name = "AVDD_HDMI_PLL_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo9 { regulator-name = "VDDIO_RX_DDR_2.85V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; ldo_rtc { regulator-name = "VCC_BATT"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; /* LM95245 temperature sensor */ temp-sensor@4c { compatible = "national,lm95245"; reg = <0x4c>; }; }; pmc@7000e400 { nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; core-supply = <&vdd_core>; /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ i2c-thermtrip { nvidia,i2c-controller-id = <3>; nvidia,bus-addr = <0x34>; nvidia,reg-addr = <0x14>; nvidia,reg-data = <0x8>; }; }; memory-controller@7000f400 { emc-table@83250 { reg = <83250>; compatible = "nvidia,tegra20-emc-table"; clock-frequency = <83250>; nvidia,emc-registers = <0x00000005 0x00000011 0x00000004 0x00000002 0x00000004 0x00000004 0x00000001 0x0000000a 0x00000002 0x00000002 0x00000001 0x00000001 0x00000003 0x00000004 0x00000003 0x00000009 0x0000000c 0x0000025f 0x00000000 0x00000003 0x00000003 0x00000002 0x00000002 0x00000001 0x00000008 0x000000c8 0x00000003 0x00000005 0x00000003 0x0000000c 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0x00520006 0x00000010 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; }; emc-table@133200 { reg = <133200>; compatible = "nvidia,tegra20-emc-table"; clock-frequency = <133200>; nvidia,emc-registers = <0x00000008 0x00000019 0x00000006 0x00000002 0x00000004 0x00000004 0x00000001 0x0000000a 0x00000002 0x00000002 0x00000002 0x00000001 0x00000003 0x00000004 0x00000003 0x00000009 0x0000000c 0x0000039f 0x00000000 0x00000003 0x00000003 0x00000002 0x00000002 0x00000001 0x00000008 0x000000c8 0x00000003 0x00000007 0x00000003 0x0000000c 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0x00510006 0x00000010 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; }; emc-table@166500 { reg = <166500>; compatible = "nvidia,tegra20-emc-table"; clock-frequency = <166500>; nvidia,emc-registers = <0x0000000a 0x00000021 0x00000008 0x00000003 0x00000004 0x00000004 0x00000002 0x0000000a 0x00000003 0x00000003 0x00000002 0x00000001 0x00000003 0x00000004 0x00000003 0x00000009 0x0000000c 0x000004df 0x00000000 0x00000003 0x00000003 0x00000003 0x00000003 0x00000001 0x00000009 0x000000c8 0x00000003 0x00000009 0x00000004 0x0000000c 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0x004f0006 0x00000010 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; }; emc-table@333000 { reg = <333000>; compatible = "nvidia,tegra20-emc-table"; clock-frequency = <333000>; nvidia,emc-registers = <0x00000014 0x00000041 0x0000000f 0x00000005 0x00000004 0x00000005 0x00000003 0x0000000a 0x00000005 0x00000005 0x00000004 0x00000001 0x00000003 0x00000004 0x00000003 0x00000009 0x0000000c 0x000009ff 0x00000000 0x00000003 0x00000003 0x00000005 0x00000005 0x00000001 0x0000000e 0x000000c8 0x00000003 0x00000011 0x00000006 0x0000000c 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0x00380006 0x00000010 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ usb@c5004000 { status = "okay"; #address-cells = <1>; #size-cells = <0>; ethernet@1 { compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; }; usb-phy@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; vbus-supply = <®_lan_v_bus>; }; clk32k_in: clock-xtal3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; opp-table-emc { /delete-node/ opp-760000000; }; reg_lan_v_bus: regulator-lan-v-bus { compatible = "regulator-fixed"; regulator-name = "LAN_V_BUS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; sound { compatible = "nvidia,tegra-audio-wm9712-colibri_t20", "nvidia,tegra-audio-wm9712"; nvidia,model = "Toradex Colibri T20"; nvidia,audio-routing = "Headphone", "HPOUTL", "Headphone", "HPOUTR", "LineIn", "LINEINL", "LineIn", "LINEINR", "Mic", "MIC1"; nvidia,ac97-controller = <&tegra_ac97>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; |