Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 | // SPDX-License-Identifier: GPL-2.0+ /* * Microchip ENC28J60 ethernet driver (MAC + PHY) * * Copyright (C) 2007 Eurek srl * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com> * based on enc28j60.c written by David Anders for 2.4 kernel version * * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $ */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/fcntl.h> #include <linux/interrupt.h> #include <linux/property.h> #include <linux/string.h> #include <linux/errno.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/ethtool.h> #include <linux/tcp.h> #include <linux/skbuff.h> #include <linux/delay.h> #include <linux/spi/spi.h> #include "enc28j60_hw.h" #define DRV_NAME "enc28j60" #define DRV_VERSION "1.02" #define SPI_OPLEN 1 #define ENC28J60_MSG_DEFAULT \ (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK) /* Buffer size required for the largest SPI transfer (i.e., reading a * frame). */ #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN) #define TX_TIMEOUT (4 * HZ) /* Max TX retries in case of collision as suggested by errata datasheet */ #define MAX_TX_RETRYCOUNT 16 enum { RXFILTER_NORMAL, RXFILTER_MULTI, RXFILTER_PROMISC }; /* Driver local data */ struct enc28j60_net { struct net_device *netdev; struct spi_device *spi; struct mutex lock; struct sk_buff *tx_skb; struct work_struct tx_work; struct work_struct setrx_work; struct work_struct restart_work; u8 bank; /* current register bank selected */ u16 next_pk_ptr; /* next packet pointer within FIFO */ u16 max_pk_counter; /* statistics: max packet counter */ u16 tx_retry_count; bool hw_enable; bool full_duplex; int rxfilter; u32 msg_enable; u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN]; }; /* use ethtool to change the level for any given device */ static struct { u32 msg_enable; } debug = { -1 }; /* * SPI read buffer * Wait for the SPI transfer and copy received data to destination. */ static int spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) { struct device *dev = &priv->spi->dev; u8 *rx_buf = priv->spi_transfer_buf + 4; u8 *tx_buf = priv->spi_transfer_buf; struct spi_transfer tx = { .tx_buf = tx_buf, .len = SPI_OPLEN, }; struct spi_transfer rx = { .rx_buf = rx_buf, .len = len, }; struct spi_message msg; int ret; tx_buf[0] = ENC28J60_READ_BUF_MEM; spi_message_init(&msg); spi_message_add_tail(&tx, &msg); spi_message_add_tail(&rx, &msg); ret = spi_sync(priv->spi, &msg); if (ret == 0) { memcpy(data, rx_buf, len); ret = msg.status; } if (ret && netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n", __func__, ret); return ret; } /* * SPI write buffer */ static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data) { struct device *dev = &priv->spi->dev; int ret; if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0) ret = -EINVAL; else { priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM; memcpy(&priv->spi_transfer_buf[1], data, len); ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1); if (ret && netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n", __func__, ret); } return ret; } /* * basic SPI read operation */ static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr) { struct device *dev = &priv->spi->dev; u8 tx_buf[2]; u8 rx_buf[4]; u8 val = 0; int ret; int slen = SPI_OPLEN; /* do dummy read if needed */ if (addr & SPRD_MASK) slen++; tx_buf[0] = op | (addr & ADDR_MASK); ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen); if (ret) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n", __func__, ret); else val = rx_buf[slen - 1]; return val; } /* * basic SPI write operation */ static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val) { struct device *dev = &priv->spi->dev; int ret; priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); priv->spi_transfer_buf[1] = val; ret = spi_write(priv->spi, priv->spi_transfer_buf, 2); if (ret && netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n", __func__, ret); return ret; } static void enc28j60_soft_reset(struct enc28j60_net *priv) { spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); /* Errata workaround #1, CLKRDY check is unreliable, * delay at least 1 ms instead */ udelay(2000); } /* * select the current register bank if necessary */ static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr) { u8 b = (addr & BANK_MASK) >> 5; /* These registers (EIE, EIR, ESTAT, ECON2, ECON1) * are present in all banks, no need to switch bank. */ if (addr >= EIE && addr <= ECON1) return; /* Clear or set each bank selection bit as needed */ if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) { if (b & ECON1_BSEL0) spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_BSEL0); else spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_BSEL0); } if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) { if (b & ECON1_BSEL1) spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_BSEL1); else spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_BSEL1); } priv->bank = b; } /* * Register access routines through the SPI bus. * Every register access comes in two flavours: * - nolock_xxx: caller needs to invoke mutex_lock, usually to access * atomically more than one register * - locked_xxx: caller doesn't need to invoke mutex_lock, single access * * Some registers can be accessed through the bit field clear and * bit field set to avoid a read modify write cycle. */ /* * Register bit field Set */ static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask) { enc28j60_set_bank(priv, addr); spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask); } static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask) { mutex_lock(&priv->lock); nolock_reg_bfset(priv, addr, mask); mutex_unlock(&priv->lock); } /* * Register bit field Clear */ static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask) { enc28j60_set_bank(priv, addr); spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask); } static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask) { mutex_lock(&priv->lock); nolock_reg_bfclr(priv, addr, mask); mutex_unlock(&priv->lock); } /* * Register byte read */ static int nolock_regb_read(struct enc28j60_net *priv, u8 address) { enc28j60_set_bank(priv, address); return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); } static int locked_regb_read(struct enc28j60_net *priv, u8 address) { int ret; mutex_lock(&priv->lock); ret = nolock_regb_read(priv, address); mutex_unlock(&priv->lock); return ret; } /* * Register word read */ static int nolock_regw_read(struct enc28j60_net *priv, u8 address) { int rl, rh; enc28j60_set_bank(priv, address); rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1); return (rh << 8) | rl; } static int locked_regw_read(struct enc28j60_net *priv, u8 address) { int ret; mutex_lock(&priv->lock); ret = nolock_regw_read(priv, address); mutex_unlock(&priv->lock); return ret; } /* * Register byte write */ static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data) { enc28j60_set_bank(priv, address); spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data); } static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data) { mutex_lock(&priv->lock); nolock_regb_write(priv, address, data); mutex_unlock(&priv->lock); } /* * Register word write */ static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data) { enc28j60_set_bank(priv, address); spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data); spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1, (u8) (data >> 8)); } static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data) { mutex_lock(&priv->lock); nolock_regw_write(priv, address, data); mutex_unlock(&priv->lock); } /* * Buffer memory read * Select the starting address and execute a SPI buffer read. */ static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len, u8 *data) { mutex_lock(&priv->lock); nolock_regw_write(priv, ERDPTL, addr); #ifdef CONFIG_ENC28J60_WRITEVERIFY if (netif_msg_drv(priv)) { struct device *dev = &priv->spi->dev; u16 reg; reg = nolock_regw_read(priv, ERDPTL); if (reg != addr) dev_printk(KERN_DEBUG, dev, "%s() error writing ERDPT (0x%04x - 0x%04x)\n", __func__, reg, addr); } #endif spi_read_buf(priv, len, data); mutex_unlock(&priv->lock); } /* * Write packet to enc28j60 TX buffer memory */ static void enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data) { struct device *dev = &priv->spi->dev; mutex_lock(&priv->lock); /* Set the write pointer to start of transmit buffer area */ nolock_regw_write(priv, EWRPTL, TXSTART_INIT); #ifdef CONFIG_ENC28J60_WRITEVERIFY if (netif_msg_drv(priv)) { u16 reg; reg = nolock_regw_read(priv, EWRPTL); if (reg != TXSTART_INIT) dev_printk(KERN_DEBUG, dev, "%s() ERWPT:0x%04x != 0x%04x\n", __func__, reg, TXSTART_INIT); } #endif /* Set the TXND pointer to correspond to the packet size given */ nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len); /* write per-packet control byte */ spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00); if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "%s() after control byte ERWPT:0x%04x\n", __func__, nolock_regw_read(priv, EWRPTL)); /* copy the packet into the transmit buffer */ spi_write_buf(priv, len, data); if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "%s() after write packet ERWPT:0x%04x, len=%d\n", __func__, nolock_regw_read(priv, EWRPTL), len); mutex_unlock(&priv->lock); } static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) { struct device *dev = &priv->spi->dev; unsigned long timeout = jiffies + msecs_to_jiffies(20); /* 20 msec timeout read */ while ((nolock_regb_read(priv, reg) & mask) != val) { if (time_after(jiffies, timeout)) { if (netif_msg_drv(priv)) dev_dbg(dev, "reg %02x ready timeout!\n", reg); return -ETIMEDOUT; } cpu_relax(); } return 0; } /* * Wait until the PHY operation is complete. */ static int wait_phy_ready(struct enc28j60_net *priv) { return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1; } /* * PHY register read * PHY registers are not accessed directly, but through the MII. */ static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address) { u16 ret; mutex_lock(&priv->lock); /* set the PHY register address */ nolock_regb_write(priv, MIREGADR, address); /* start the register read operation */ nolock_regb_write(priv, MICMD, MICMD_MIIRD); /* wait until the PHY read completes */ wait_phy_ready(priv); /* quit reading */ nolock_regb_write(priv, MICMD, 0x00); /* return the data */ ret = nolock_regw_read(priv, MIRDL); mutex_unlock(&priv->lock); return ret; } static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data) { int ret; mutex_lock(&priv->lock); /* set the PHY register address */ nolock_regb_write(priv, MIREGADR, address); /* write the PHY data */ nolock_regw_write(priv, MIWRL, data); /* wait until the PHY write completes and return */ ret = wait_phy_ready(priv); mutex_unlock(&priv->lock); return ret; } /* * Program the hardware MAC address from dev->dev_addr. */ static int enc28j60_set_hw_macaddr(struct net_device *ndev) { int ret; struct enc28j60_net *priv = netdev_priv(ndev); struct device *dev = &priv->spi->dev; mutex_lock(&priv->lock); if (!priv->hw_enable) { if (netif_msg_drv(priv)) dev_info(dev, "%s: Setting MAC address to %pM\n", ndev->name, ndev->dev_addr); /* NOTE: MAC address in ENC28J60 is byte-backward */ nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]); nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]); nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]); nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]); nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]); nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]); ret = 0; } else { if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() Hardware must be disabled to set Mac address\n", __func__); ret = -EBUSY; } mutex_unlock(&priv->lock); return ret; } /* * Store the new hardware address in dev->dev_addr, and update the MAC. */ static int enc28j60_set_mac_address(struct net_device *dev, void *addr) { struct sockaddr *address = addr; if (netif_running(dev)) return -EBUSY; if (!is_valid_ether_addr(address->sa_data)) return -EADDRNOTAVAIL; eth_hw_addr_set(dev, address->sa_data); return enc28j60_set_hw_macaddr(dev); } /* * Debug routine to dump useful register contents */ static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg) { struct device *dev = &priv->spi->dev; mutex_lock(&priv->lock); dev_printk(KERN_DEBUG, dev, " %s\n" "HwRevID: 0x%02x\n" "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n" " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" "MAC : MACON1 MACON3 MACON4\n" " 0x%02x 0x%02x 0x%02x\n" "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n" " 0x%04x 0x%04x 0x%04x 0x%04x " "0x%02x 0x%02x 0x%04x\n" "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n" " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n", msg, nolock_regb_read(priv, EREVID), nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR), nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1), nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4), nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL), nolock_regw_read(priv, ERXWRPTL), nolock_regw_read(priv, ERXRDPTL), nolock_regb_read(priv, ERXFCON), nolock_regb_read(priv, EPKTCNT), nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL), nolock_regw_read(priv, ETXNDL), nolock_regb_read(priv, MACLCON1), nolock_regb_read(priv, MACLCON2), nolock_regb_read(priv, MAPHSUP)); mutex_unlock(&priv->lock); } /* * ERXRDPT need to be set always at odd addresses, refer to errata datasheet */ static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end) { u16 erxrdpt; if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end)) erxrdpt = end; else erxrdpt = next_packet_ptr - 1; return erxrdpt; } /* * Calculate wrap around when reading beyond the end of the RX buffer */ static u16 rx_packet_start(u16 ptr) { if (ptr + RSV_SIZE > RXEND_INIT) return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1); else return ptr + RSV_SIZE; } static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end) { struct device *dev = &priv->spi->dev; u16 erxrdpt; if (start > 0x1FFF || end > 0x1FFF || start > end) { if (netif_msg_drv(priv)) dev_err(dev, "%s(%d, %d) RXFIFO bad parameters!\n", __func__, start, end); return; } /* set receive buffer start + end */ priv->next_pk_ptr = start; nolock_regw_write(priv, ERXSTL, start); erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end); nolock_regw_write(priv, ERXRDPTL, erxrdpt); nolock_regw_write(priv, ERXNDL, end); } static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end) { struct device *dev = &priv->spi->dev; if (start > 0x1FFF || end > 0x1FFF || start > end) { if (netif_msg_drv(priv)) dev_err(dev, "%s(%d, %d) TXFIFO bad parameters!\n", __func__, start, end); return; } /* set transmit buffer start + end */ nolock_regw_write(priv, ETXSTL, start); nolock_regw_write(priv, ETXNDL, end); } /* * Low power mode shrinks power consumption about 100x, so we'd like * the chip to be in that mode whenever it's inactive. (However, we * can't stay in low power mode during suspend with WOL active.) */ static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low) { struct device *dev = &priv->spi->dev; if (netif_msg_drv(priv)) dev_dbg(dev, "%s power...\n", is_low ? "low" : "high"); mutex_lock(&priv->lock); if (is_low) { nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0); poll_ready(priv, ECON1, ECON1_TXRTS, 0); /* ECON2_VRPS was set during initialization */ nolock_reg_bfset(priv, ECON2, ECON2_PWRSV); } else { nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV); poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY); /* caller sets ECON1_RXEN */ } mutex_unlock(&priv->lock); } static int enc28j60_hw_init(struct enc28j60_net *priv) { struct device *dev = &priv->spi->dev; u8 reg; if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() - %s\n", __func__, priv->full_duplex ? "FullDuplex" : "HalfDuplex"); mutex_lock(&priv->lock); /* first reset the chip */ enc28j60_soft_reset(priv); /* Clear ECON1 */ spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); priv->bank = 0; priv->hw_enable = false; priv->tx_retry_count = 0; priv->max_pk_counter = 0; priv->rxfilter = RXFILTER_NORMAL; /* enable address auto increment and voltage regulator powersave */ nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS); nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); mutex_unlock(&priv->lock); /* * Check the RevID. * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or * damaged. */ reg = locked_regb_read(priv, EREVID); if (netif_msg_drv(priv)) dev_info(dev, "chip RevID: 0x%02x\n", reg); if (reg == 0x00 || reg == 0xff) { if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "%s() Invalid RevId %d\n", __func__, reg); return 0; } /* default filter mode: (unicast OR broadcast) AND crc valid */ locked_regb_write(priv, ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); /* enable MAC receive */ locked_regb_write(priv, MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); /* enable automatic padding and CRC operations */ if (priv->full_duplex) { locked_regb_write(priv, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); /* set inter-frame gap (non-back-to-back) */ locked_regb_write(priv, MAIPGL, 0x12); /* set inter-frame gap (back-to-back) */ locked_regb_write(priv, MABBIPG, 0x15); } else { locked_regb_write(priv, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */ /* set inter-frame gap (non-back-to-back) */ locked_regw_write(priv, MAIPGL, 0x0C12); /* set inter-frame gap (back-to-back) */ locked_regb_write(priv, MABBIPG, 0x12); } /* * MACLCON1 (default) * MACLCON2 (default) * Set the maximum packet size which the controller will accept. */ locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN); /* Configure LEDs */ if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE)) return 0; if (priv->full_duplex) { if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD)) return 0; if (!enc28j60_phy_write(priv, PHCON2, 0x00)) return 0; } else { if (!enc28j60_phy_write(priv, PHCON1, 0x00)) return 0; if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS)) return 0; } if (netif_msg_hw(priv)) enc28j60_dump_regs(priv, "Hw initialized."); return 1; } static void enc28j60_hw_enable(struct enc28j60_net *priv) { struct device *dev = &priv->spi->dev; /* enable interrupts */ if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "%s() enabling interrupts.\n", __func__); enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE); mutex_lock(&priv->lock); nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF); nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE | EIE_TXIE | EIE_TXERIE | EIE_RXERIE); /* enable receive logic */ nolock_reg_bfset(priv, ECON1, ECON1_RXEN); priv->hw_enable = true; mutex_unlock(&priv->lock); } static void enc28j60_hw_disable(struct enc28j60_net *priv) { mutex_lock(&priv->lock); /* disable interrupts and packet reception */ nolock_regb_write(priv, EIE, 0x00); nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); priv->hw_enable = false; mutex_unlock(&priv->lock); } static int enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex) { struct enc28j60_net *priv = netdev_priv(ndev); int ret = 0; if (!priv->hw_enable) { /* link is in low power mode now; duplex setting * will take effect on next enc28j60_hw_init(). */ if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) priv->full_duplex = (duplex == DUPLEX_FULL); else { if (netif_msg_link(priv)) netdev_warn(ndev, "unsupported link setting\n"); ret = -EOPNOTSUPP; } } else { if (netif_msg_link(priv)) netdev_warn(ndev, "Warning: hw must be disabled to set link mode\n"); ret = -EBUSY; } return ret; } /* * Read the Transmit Status Vector */ static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE]) { struct device *dev = &priv->spi->dev; int endptr; endptr = locked_regw_read(priv, ETXNDL); if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "reading TSV at addr:0x%04x\n", endptr + 1); enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv); } static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg, u8 tsv[TSV_SIZE]) { struct device *dev = &priv->spi->dev; u16 tmp1, tmp2; dev_printk(KERN_DEBUG, dev, "%s - TSV:\n", msg); tmp1 = tsv[1]; tmp1 <<= 8; tmp1 |= tsv[0]; tmp2 = tsv[5]; tmp2 <<= 8; tmp2 |= tsv[4]; dev_printk(KERN_DEBUG, dev, "ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2); dev_printk(KERN_DEBUG, dev, "TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE), TSV_GETBIT(tsv, TSV_TXCRCERROR), TSV_GETBIT(tsv, TSV_TXLENCHKERROR), TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE)); dev_printk(KERN_DEBUG, dev, "Multicast: %d, Broadcast: %d, PacketDefer: %d, ExDefer: %d\n", TSV_GETBIT(tsv, TSV_TXMULTICAST), TSV_GETBIT(tsv, TSV_TXBROADCAST), TSV_GETBIT(tsv, TSV_TXPACKETDEFER), TSV_GETBIT(tsv, TSV_TXEXDEFER)); dev_printk(KERN_DEBUG, dev, "ExCollision: %d, LateCollision: %d, Giant: %d, Underrun: %d\n", TSV_GETBIT(tsv, TSV_TXEXCOLLISION), TSV_GETBIT(tsv, TSV_TXLATECOLLISION), TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN)); dev_printk(KERN_DEBUG, dev, "ControlFrame: %d, PauseFrame: %d, BackPressApp: %d, VLanTagFrame: %d\n", TSV_GETBIT(tsv, TSV_TXCONTROLFRAME), TSV_GETBIT(tsv, TSV_TXPAUSEFRAME), TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP), TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME)); } /* * Receive Status vector */ static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg, u16 pk_ptr, int len, u16 sts) { struct device *dev = &priv->spi->dev; dev_printk(KERN_DEBUG, dev, "%s - NextPk: 0x%04x - RSV:\n", msg, pk_ptr); dev_printk(KERN_DEBUG, dev, "ByteCount: %d, DribbleNibble: %d\n", len, RSV_GETBIT(sts, RSV_DRIBBLENIBBLE)); dev_printk(KERN_DEBUG, dev, "RxOK: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK), RSV_GETBIT(sts, RSV_CRCERROR), RSV_GETBIT(sts, RSV_LENCHECKERR), RSV_GETBIT(sts, RSV_LENOUTOFRANGE)); dev_printk(KERN_DEBUG, dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n", RSV_GETBIT(sts, RSV_RXMULTICAST), RSV_GETBIT(sts, RSV_RXBROADCAST), RSV_GETBIT(sts, RSV_RXLONGEVDROPEV), RSV_GETBIT(sts, RSV_CARRIEREV)); dev_printk(KERN_DEBUG, dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n", RSV_GETBIT(sts, RSV_RXCONTROLFRAME), RSV_GETBIT(sts, RSV_RXPAUSEFRAME), RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE), RSV_GETBIT(sts, RSV_RXTYPEVLAN)); } static void dump_packet(const char *msg, int len, const char *data) { printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len); print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1, data, len, true); } /* * Hardware receive function. * Read the buffer memory, update the FIFO pointer to free the buffer, * check the status vector and decrement the packet counter. */ static void enc28j60_hw_rx(struct net_device *ndev) { struct enc28j60_net *priv = netdev_priv(ndev); struct device *dev = &priv->spi->dev; struct sk_buff *skb = NULL; u16 erxrdpt, next_packet, rxstat; u8 rsv[RSV_SIZE]; int len; if (netif_msg_rx_status(priv)) netdev_printk(KERN_DEBUG, ndev, "RX pk_addr:0x%04x\n", priv->next_pk_ptr); if (unlikely(priv->next_pk_ptr > RXEND_INIT)) { if (netif_msg_rx_err(priv)) netdev_err(ndev, "%s() Invalid packet address!! 0x%04x\n", __func__, priv->next_pk_ptr); /* packet address corrupted: reset RX logic */ mutex_lock(&priv->lock); nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); nolock_reg_bfset(priv, ECON1, ECON1_RXRST); nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); nolock_reg_bfclr(priv, EIR, EIR_RXERIF); nolock_reg_bfset(priv, ECON1, ECON1_RXEN); mutex_unlock(&priv->lock); ndev->stats.rx_errors++; return; } /* Read next packet pointer and rx status vector */ enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv); next_packet = rsv[1]; next_packet <<= 8; next_packet |= rsv[0]; len = rsv[3]; len <<= 8; len |= rsv[2]; rxstat = rsv[5]; rxstat <<= 8; rxstat |= rsv[4]; if (netif_msg_rx_status(priv)) enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat); if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) { if (netif_msg_rx_err(priv)) netdev_err(ndev, "Rx Error (%04x)\n", rxstat); ndev->stats.rx_errors++; if (RSV_GETBIT(rxstat, RSV_CRCERROR)) ndev->stats.rx_crc_errors++; if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) ndev->stats.rx_frame_errors++; if (len > MAX_FRAMELEN) ndev->stats.rx_over_errors++; } else { skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN); if (!skb) { if (netif_msg_rx_err(priv)) netdev_err(ndev, "out of memory for Rx'd frame\n"); ndev->stats.rx_dropped++; } else { skb_reserve(skb, NET_IP_ALIGN); /* copy the packet from the receive buffer */ enc28j60_mem_read(priv, rx_packet_start(priv->next_pk_ptr), len, skb_put(skb, len)); if (netif_msg_pktdata(priv)) dump_packet(__func__, skb->len, skb->data); skb->protocol = eth_type_trans(skb, ndev); /* update statistics */ ndev->stats.rx_packets++; ndev->stats.rx_bytes += len; netif_rx(skb); } } /* * Move the RX read pointer to the start of the next * received packet. * This frees the memory we just read out. */ erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT); if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT:0x%04x\n", __func__, erxrdpt); mutex_lock(&priv->lock); nolock_regw_write(priv, ERXRDPTL, erxrdpt); #ifdef CONFIG_ENC28J60_WRITEVERIFY if (netif_msg_drv(priv)) { u16 reg; reg = nolock_regw_read(priv, ERXRDPTL); if (reg != erxrdpt) dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT verify error (0x%04x - 0x%04x)\n", __func__, reg, erxrdpt); } #endif priv->next_pk_ptr = next_packet; /* we are done with this packet, decrement the packet counter */ nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC); mutex_unlock(&priv->lock); } /* * Calculate free space in RxFIFO */ static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv) { struct net_device *ndev = priv->netdev; int epkcnt, erxst, erxnd, erxwr, erxrd; int free_space; mutex_lock(&priv->lock); epkcnt = nolock_regb_read(priv, EPKTCNT); if (epkcnt >= 255) free_space = -1; else { erxst = nolock_regw_read(priv, ERXSTL); erxnd = nolock_regw_read(priv, ERXNDL); erxwr = nolock_regw_read(priv, ERXWRPTL); erxrd = nolock_regw_read(priv, ERXRDPTL); if (erxwr > erxrd) free_space = (erxnd - erxst) - (erxwr - erxrd); else if (erxwr == erxrd) free_space = (erxnd - erxst); else free_space = erxrd - erxwr - 1; } mutex_unlock(&priv->lock); if (netif_msg_rx_status(priv)) netdev_printk(KERN_DEBUG, ndev, "%s() free_space = %d\n", __func__, free_space); return free_space; } /* * Access the PHY to determine link status */ static void enc28j60_check_link_status(struct net_device *ndev) { struct enc28j60_net *priv = netdev_priv(ndev); struct device *dev = &priv->spi->dev; u16 reg; int duplex; reg = enc28j60_phy_read(priv, PHSTAT2); if (netif_msg_hw(priv)) dev_printk(KERN_DEBUG, dev, "%s() PHSTAT1: %04x, PHSTAT2: %04x\n", __func__, enc28j60_phy_read(priv, PHSTAT1), reg); duplex = reg & PHSTAT2_DPXSTAT; if (reg & PHSTAT2_LSTAT) { netif_carrier_on(ndev); if (netif_msg_ifup(priv)) netdev_info(ndev, "link up - %s\n", duplex ? "Full duplex" : "Half duplex"); } else { if (netif_msg_ifdown(priv)) netdev_info(ndev, "link down\n"); netif_carrier_off(ndev); } } static void enc28j60_tx_clear(struct net_device *ndev, bool err) { struct enc28j60_net *priv = netdev_priv(ndev); if (err) ndev->stats.tx_errors++; else ndev->stats.tx_packets++; if (priv->tx_skb) { if (!err) ndev->stats.tx_bytes += priv->tx_skb->len; dev_kfree_skb(priv->tx_skb); priv->tx_skb = NULL; } locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); netif_wake_queue(ndev); } /* * RX handler * Ignore PKTIF because is unreliable! (Look at the errata datasheet) * Check EPKTCNT is the suggested workaround. * We don't need to clear interrupt flag, automatically done when * enc28j60_hw_rx() decrements the packet counter. * Returns how many packet processed. */ static int enc28j60_rx_interrupt(struct net_device *ndev) { struct enc28j60_net *priv = netdev_priv(ndev); int pk_counter, ret; pk_counter = locked_regb_read(priv, EPKTCNT); if (pk_counter && netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intRX, pk_cnt: %d\n", pk_counter); if (pk_counter > priv->max_pk_counter) { /* update statistics */ priv->max_pk_counter = pk_counter; if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1) netdev_printk(KERN_DEBUG, ndev, "RX max_pk_cnt: %d\n", priv->max_pk_counter); } ret = pk_counter; while (pk_counter-- > 0) enc28j60_hw_rx(ndev); return ret; } static irqreturn_t enc28j60_irq(int irq, void *dev_id) { struct enc28j60_net *priv = dev_id; struct net_device *ndev = priv->netdev; int intflags, loop; /* disable further interrupts */ locked_reg_bfclr(priv, EIE, EIE_INTIE); do { loop = 0; intflags = locked_regb_read(priv, EIR); /* DMA interrupt handler (not currently used) */ if ((intflags & EIR_DMAIF) != 0) { loop++; if (netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intDMA(%d)\n", loop); locked_reg_bfclr(priv, EIR, EIR_DMAIF); } /* LINK changed handler */ if ((intflags & EIR_LINKIF) != 0) { loop++; if (netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intLINK(%d)\n", loop); enc28j60_check_link_status(ndev); /* read PHIR to clear the flag */ enc28j60_phy_read(priv, PHIR); } /* TX complete handler */ if (((intflags & EIR_TXIF) != 0) && ((intflags & EIR_TXERIF) == 0)) { bool err = false; loop++; if (netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intTX(%d)\n", loop); priv->tx_retry_count = 0; if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) { if (netif_msg_tx_err(priv)) netdev_err(ndev, "Tx Error (aborted)\n"); err = true; } if (netif_msg_tx_done(priv)) { u8 tsv[TSV_SIZE]; enc28j60_read_tsv(priv, tsv); enc28j60_dump_tsv(priv, "Tx Done", tsv); } enc28j60_tx_clear(ndev, err); locked_reg_bfclr(priv, EIR, EIR_TXIF); } /* TX Error handler */ if ((intflags & EIR_TXERIF) != 0) { u8 tsv[TSV_SIZE]; loop++; if (netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intTXErr(%d)\n", loop); locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); enc28j60_read_tsv(priv, tsv); if (netif_msg_tx_err(priv)) enc28j60_dump_tsv(priv, "Tx Error", tsv); /* Reset TX logic */ mutex_lock(&priv->lock); nolock_reg_bfset(priv, ECON1, ECON1_TXRST); nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); mutex_unlock(&priv->lock); /* Transmit Late collision check for retransmit */ if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) { if (netif_msg_tx_err(priv)) netdev_printk(KERN_DEBUG, ndev, "LateCollision TXErr (%d)\n", priv->tx_retry_count); if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT) locked_reg_bfset(priv, ECON1, ECON1_TXRTS); else enc28j60_tx_clear(ndev, true); } else enc28j60_tx_clear(ndev, true); locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF); } /* RX Error handler */ if ((intflags & EIR_RXERIF) != 0) { loop++; if (netif_msg_intr(priv)) netdev_printk(KERN_DEBUG, ndev, "intRXErr(%d)\n", loop); /* Check free FIFO space to flag RX overrun */ if (enc28j60_get_free_rxfifo(priv) <= 0) { if (netif_msg_rx_err(priv)) netdev_printk(KERN_DEBUG, ndev, "RX Overrun\n"); ndev->stats.rx_dropped++; } locked_reg_bfclr(priv, EIR, EIR_RXERIF); } /* RX handler */ if (enc28j60_rx_interrupt(ndev)) loop++; } while (loop); /* re-enable interrupts */ locked_reg_bfset(priv, EIE, EIE_INTIE); return IRQ_HANDLED; } /* * Hardware transmit function. * Fill the buffer memory and send the contents of the transmit buffer * onto the network */ static void enc28j60_hw_tx(struct enc28j60_net *priv) { struct net_device *ndev = priv->netdev; BUG_ON(!priv->tx_skb); if (netif_msg_tx_queued(priv)) netdev_printk(KERN_DEBUG, ndev, "Tx Packet Len:%d\n", priv->tx_skb->len); if (netif_msg_pktdata(priv)) dump_packet(__func__, priv->tx_skb->len, priv->tx_skb->data); enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data); #ifdef CONFIG_ENC28J60_WRITEVERIFY /* readback and verify written data */ if (netif_msg_drv(priv)) { struct device *dev = &priv->spi->dev; int test_len, k; u8 test_buf[64]; /* limit the test to the first 64 bytes */ int okflag; test_len = priv->tx_skb->len; if (test_len > sizeof(test_buf)) test_len = sizeof(test_buf); /* + 1 to skip control byte */ enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf); okflag = 1; for (k = 0; k < test_len; k++) { if (priv->tx_skb->data[k] != test_buf[k]) { dev_printk(KERN_DEBUG, dev, "Error, %d location differ: 0x%02x-0x%02x\n", k, priv->tx_skb->data[k], test_buf[k]); okflag = 0; } } if (!okflag) dev_printk(KERN_DEBUG, dev, "Tx write buffer, verify ERROR!\n"); } #endif /* set TX request flag */ locked_reg_bfset(priv, ECON1, ECON1_TXRTS); } static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); /* If some error occurs while trying to transmit this * packet, you should return '1' from this function. * In such a case you _may not_ do anything to the * SKB, it is still owned by the network queueing * layer when an error is returned. This means you * may not modify any SKB fields, you may not free * the SKB, etc. */ netif_stop_queue(dev); /* Remember the skb for deferred processing */ priv->tx_skb = skb; schedule_work(&priv->tx_work); return NETDEV_TX_OK; } static void enc28j60_tx_work_handler(struct work_struct *work) { struct enc28j60_net *priv = container_of(work, struct enc28j60_net, tx_work); /* actual delivery of data */ enc28j60_hw_tx(priv); } static void enc28j60_tx_timeout(struct net_device *ndev, unsigned int txqueue) { struct enc28j60_net *priv = netdev_priv(ndev); if (netif_msg_timer(priv)) netdev_err(ndev, "tx timeout\n"); ndev->stats.tx_errors++; /* can't restart safely under softirq */ schedule_work(&priv->restart_work); } /* * Open/initialize the board. This is called (in the current kernel) * sometime after booting when the 'ifconfig' program is run. * * This routine should set everything up anew at each open, even * registers that "should" only need to be set once at boot, so that * there is non-reboot way to recover if something goes wrong. */ static int enc28j60_net_open(struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); if (!is_valid_ether_addr(dev->dev_addr)) { if (netif_msg_ifup(priv)) netdev_err(dev, "invalid MAC address %pM\n", dev->dev_addr); return -EADDRNOTAVAIL; } /* Reset the hardware here (and take it out of low power mode) */ enc28j60_lowpower(priv, false); enc28j60_hw_disable(priv); if (!enc28j60_hw_init(priv)) { if (netif_msg_ifup(priv)) netdev_err(dev, "hw_reset() failed\n"); return -EINVAL; } /* Update the MAC address (in case user has changed it) */ enc28j60_set_hw_macaddr(dev); /* Enable interrupts */ enc28j60_hw_enable(priv); /* check link status */ enc28j60_check_link_status(dev); /* We are now ready to accept transmit requests from * the queueing layer of the networking. */ netif_start_queue(dev); return 0; } /* The inverse routine to net_open(). */ static int enc28j60_net_close(struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); enc28j60_hw_disable(priv); enc28j60_lowpower(priv, true); netif_stop_queue(dev); return 0; } /* * Set or clear the multicast filter for this adapter * num_addrs == -1 Promiscuous mode, receive all packets * num_addrs == 0 Normal mode, filter out multicast packets * num_addrs > 0 Multicast mode, receive normal and MC packets */ static void enc28j60_set_multicast_list(struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); int oldfilter = priv->rxfilter; if (dev->flags & IFF_PROMISC) { if (netif_msg_link(priv)) netdev_info(dev, "promiscuous mode\n"); priv->rxfilter = RXFILTER_PROMISC; } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { if (netif_msg_link(priv)) netdev_info(dev, "%smulticast mode\n", (dev->flags & IFF_ALLMULTI) ? "all-" : ""); priv->rxfilter = RXFILTER_MULTI; } else { if (netif_msg_link(priv)) netdev_info(dev, "normal mode\n"); priv->rxfilter = RXFILTER_NORMAL; } if (oldfilter != priv->rxfilter) schedule_work(&priv->setrx_work); } static void enc28j60_setrx_work_handler(struct work_struct *work) { struct enc28j60_net *priv = container_of(work, struct enc28j60_net, setrx_work); struct device *dev = &priv->spi->dev; if (priv->rxfilter == RXFILTER_PROMISC) { if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "promiscuous mode\n"); locked_regb_write(priv, ERXFCON, 0x00); } else if (priv->rxfilter == RXFILTER_MULTI) { if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "multicast mode\n"); locked_regb_write(priv, ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN | ERXFCON_MCEN); } else { if (netif_msg_drv(priv)) dev_printk(KERN_DEBUG, dev, "normal mode\n"); locked_regb_write(priv, ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); } } static void enc28j60_restart_work_handler(struct work_struct *work) { struct enc28j60_net *priv = container_of(work, struct enc28j60_net, restart_work); struct net_device *ndev = priv->netdev; int ret; rtnl_lock(); if (netif_running(ndev)) { enc28j60_net_close(ndev); ret = enc28j60_net_open(ndev); if (unlikely(ret)) { netdev_info(ndev, "could not restart %d\n", ret); dev_close(ndev); } } rtnl_unlock(); } /* ......................... ETHTOOL SUPPORT ........................... */ static void enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) { strscpy(info->driver, DRV_NAME, sizeof(info->driver)); strscpy(info->version, DRV_VERSION, sizeof(info->version)); strscpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); } static int enc28j60_get_link_ksettings(struct net_device *dev, struct ethtool_link_ksettings *cmd) { struct enc28j60_net *priv = netdev_priv(dev); ethtool_link_ksettings_zero_link_mode(cmd, supported); ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Half); ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Full); ethtool_link_ksettings_add_link_mode(cmd, supported, TP); cmd->base.speed = SPEED_10; cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; cmd->base.port = PORT_TP; cmd->base.autoneg = AUTONEG_DISABLE; return 0; } static int enc28j60_set_link_ksettings(struct net_device *dev, const struct ethtool_link_ksettings *cmd) { return enc28j60_setlink(dev, cmd->base.autoneg, cmd->base.speed, cmd->base.duplex); } static u32 enc28j60_get_msglevel(struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); return priv->msg_enable; } static void enc28j60_set_msglevel(struct net_device *dev, u32 val) { struct enc28j60_net *priv = netdev_priv(dev); priv->msg_enable = val; } static const struct ethtool_ops enc28j60_ethtool_ops = { .get_drvinfo = enc28j60_get_drvinfo, .get_msglevel = enc28j60_get_msglevel, .set_msglevel = enc28j60_set_msglevel, .get_link_ksettings = enc28j60_get_link_ksettings, .set_link_ksettings = enc28j60_set_link_ksettings, }; static int enc28j60_chipset_init(struct net_device *dev) { struct enc28j60_net *priv = netdev_priv(dev); return enc28j60_hw_init(priv); } static const struct net_device_ops enc28j60_netdev_ops = { .ndo_open = enc28j60_net_open, .ndo_stop = enc28j60_net_close, .ndo_start_xmit = enc28j60_send_packet, .ndo_set_rx_mode = enc28j60_set_multicast_list, .ndo_set_mac_address = enc28j60_set_mac_address, .ndo_tx_timeout = enc28j60_tx_timeout, .ndo_validate_addr = eth_validate_addr, }; static int enc28j60_probe(struct spi_device *spi) { struct net_device *dev; struct enc28j60_net *priv; int ret = 0; if (netif_msg_drv(&debug)) dev_info(&spi->dev, "Ethernet driver %s loaded\n", DRV_VERSION); dev = alloc_etherdev(sizeof(struct enc28j60_net)); if (!dev) { ret = -ENOMEM; goto error_alloc; } priv = netdev_priv(dev); priv->netdev = dev; /* priv to netdev reference */ priv->spi = spi; /* priv to spi reference */ priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT); mutex_init(&priv->lock); INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler); INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler); INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler); spi_set_drvdata(spi, priv); /* spi to priv reference */ SET_NETDEV_DEV(dev, &spi->dev); if (!enc28j60_chipset_init(dev)) { if (netif_msg_probe(priv)) dev_info(&spi->dev, "chip not found\n"); ret = -EIO; goto error_irq; } if (device_get_ethdev_address(&spi->dev, dev)) eth_hw_addr_random(dev); enc28j60_set_hw_macaddr(dev); /* Board setup must set the relevant edge trigger type; * level triggers won't currently work. */ ret = request_threaded_irq(spi->irq, NULL, enc28j60_irq, IRQF_ONESHOT, DRV_NAME, priv); if (ret < 0) { if (netif_msg_probe(priv)) dev_err(&spi->dev, "request irq %d failed (ret = %d)\n", spi->irq, ret); goto error_irq; } dev->if_port = IF_PORT_10BASET; dev->irq = spi->irq; dev->netdev_ops = &enc28j60_netdev_ops; dev->watchdog_timeo = TX_TIMEOUT; dev->ethtool_ops = &enc28j60_ethtool_ops; enc28j60_lowpower(priv, true); ret = register_netdev(dev); if (ret) { if (netif_msg_probe(priv)) dev_err(&spi->dev, "register netdev failed (ret = %d)\n", ret); goto error_register; } return 0; error_register: free_irq(spi->irq, priv); error_irq: free_netdev(dev); error_alloc: return ret; } static void enc28j60_remove(struct spi_device *spi) { struct enc28j60_net *priv = spi_get_drvdata(spi); unregister_netdev(priv->netdev); free_irq(spi->irq, priv); free_netdev(priv->netdev); } static const struct of_device_id enc28j60_dt_ids[] = { { .compatible = "microchip,enc28j60" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, enc28j60_dt_ids); static struct spi_driver enc28j60_driver = { .driver = { .name = DRV_NAME, .of_match_table = enc28j60_dt_ids, }, .probe = enc28j60_probe, .remove = enc28j60_remove, }; module_spi_driver(enc28j60_driver); MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>"); MODULE_LICENSE("GPL"); module_param_named(debug, debug.msg_enable, int, 0); MODULE_PARM_DESC(debug, "Debug verbosity level in amount of bits set (0=none, ..., 31=all)"); MODULE_ALIAS("spi:" DRV_NAME); |