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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2022 NXP */ #include <dt-bindings/clock/imx93-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/fsl,imx93-power.h> #include <dt-bindings/thermal/thermal.h> #include "imx93-pinfunc.h" / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; i2c3 = &lpi2c4; i2c4 = &lpi2c5; i2c5 = &lpi2c6; i2c6 = &lpi2c7; i2c7 = &lpi2c8; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &lpuart1; serial1 = &lpuart2; serial2 = &lpuart3; serial3 = &lpuart4; serial4 = &lpuart5; serial5 = &lpuart6; serial6 = &lpuart7; serial7 = &lpuart8; }; cpus { #address-cells = <1>; #size-cells = <0>; idle-states { entry-method = "psci"; cpu_pd_wait: cpu-pd-wait { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010033>; local-timer-stop; entry-latency-us = <10000>; exit-latency-us = <7000>; min-residency-us = <27000>; wakeup-latency-us = <15000>; }; }; A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; }; A55_1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; }; }; osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "osc_32k"; }; osc_24m: clock-osc-24m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "osc_24m"; }; clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext1"; }; pmu { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; }; gic: interrupt-controller@48000000 { compatible = "arm,gic-v3"; reg = <0 0x48000000 0 0x10000>, <0 0x48040000 0 0xc0000>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; }; thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tmu 0>; trips { cpu_alert: cpu-alert { temperature = <80000>; hysteresis = <2000>; type = "passive"; }; cpu_crit: cpu-crit { temperature = <90000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_alert>; cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; cm33: remoteproc-cm33 { compatible = "fsl,imx93-cm33"; clocks = <&clk IMX93_CLK_CM33_GATE>; status = "disabled"; }; soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x80000000>, <0x28000000 0x0 0x28000000 0x10000000>; aips1: bus@44000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x44000000 0x800000>; #address-cells = <1>; #size-cells = <1>; ranges; aonmix_ns_gpr: syscon@44210000 { compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; reg = <0x44210000 0x1000>; }; mu1: mailbox@44230000 { compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x44230000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_MU1_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; system_counter: timer@44290000 { compatible = "nxp,sysctr-timer"; reg = <0x44290000 0x30000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc_24m>; clock-names = "per"; nxp,no-divider; }; wdog1: watchdog@442d0000 { compatible = "fsl,imx93-wdt"; reg = <0x442d0000 0x10000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG1_GATE>; timeout-sec = <40>; status = "disabled"; }; wdog2: watchdog@442e0000 { compatible = "fsl,imx93-wdt"; reg = <0x442e0000 0x10000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG2_GATE>; timeout-sec = <40>; status = "disabled"; }; tpm1: pwm@44310000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44310000 0x1000>; clocks = <&clk IMX93_CLK_TPM1_GATE>; #pwm-cells = <3>; status = "disabled"; }; tpm2: pwm@44320000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44320000 0x10000>; clocks = <&clk IMX93_CLK_TPM2_GATE>; #pwm-cells = <3>; status = "disabled"; }; lpi2c1: i2c@44340000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; lpi2c2: i2c@44350000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44350000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi1: spi@44360000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x44360000 0x10000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi2: spi@44370000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x44370000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; lpuart1: serial@44380000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44380000 0x1000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg"; status = "disabled"; }; lpuart2: serial@44390000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44390000 0x1000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; status = "disabled"; }; flexcan1: can@443a0000 { compatible = "fsl,imx93-flexcan"; reg = <0x443a0000 0x10000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_BUS_AON>, <&clk IMX93_CLK_CAN1_GATE>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX93_CLK_CAN1>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; status = "disabled"; }; iomuxc: pinctrl@443c0000 { compatible = "fsl,imx93-iomuxc"; reg = <0x443c0000 0x10000>; status = "okay"; }; bbnsm: bbnsm@44440000 { compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; reg = <0x44440000 0x10000>; bbnsm_rtc: rtc { compatible = "nxp,imx93-bbnsm-rtc"; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; bbnsm_pwrkey: pwrkey { compatible = "nxp,imx93-bbnsm-pwrkey"; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; linux,code = <KEY_POWER>; }; }; clk: clock-controller@44450000 { compatible = "fsl,imx93-ccm"; reg = <0x44450000 0x10000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; clock-names = "osc_32k", "osc_24m", "clk_ext1"; status = "okay"; }; src: system-controller@44460000 { compatible = "fsl,imx93-src", "syscon"; reg = <0x44460000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges; mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; reg = <0x44461800 0x400>, <0x44464800 0x400>; #power-domain-cells = <0>; clocks = <&clk IMX93_CLK_ML_APB>, <&clk IMX93_CLK_ML>; }; mediamix: power-domain@44462400 { compatible = "fsl,imx93-src-slice"; reg = <0x44462400 0x400>, <0x44465800 0x400>; #power-domain-cells = <0>; clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, <&clk IMX93_CLK_MEDIA_APB>; }; }; anatop: anatop@44480000 { compatible = "fsl,imx93-anatop", "syscon"; reg = <0x44480000 0x2000>; }; tmu: tmu@44482000 { compatible = "fsl,qoriq-tmu"; reg = <0x44482000 0x1000>; clocks = <&clk IMX93_CLK_TMC_GATE>; little-endian; fsl,tmu-range = <0x800000da 0x800000e9 0x80000102 0x8000012a 0x80000166 0x800001a7 0x800001b6>; fsl,tmu-calibration = <0x00000000 0x0000000e 0x00000001 0x00000029 0x00000002 0x00000056 0x00000003 0x000000a2 0x00000004 0x00000116 0x00000005 0x00000195 0x00000006 0x000001b2>; #thermal-sensor-cells = <1>; }; adc1: adc@44530000 { compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; #io-channel-cells = <1>; status = "disabled"; }; }; aips2: bus@42000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x42000000 0x800000>; #address-cells = <1>; #size-cells = <1>; ranges; wakeupmix_gpr: syscon@42420000 { compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; reg = <0x42420000 0x1000>; }; mu2: mailbox@42440000 { compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x42440000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_MU2_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; wdog3: watchdog@42490000 { compatible = "fsl,imx93-wdt"; reg = <0x42490000 0x10000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG3_GATE>; timeout-sec = <40>; status = "disabled"; }; wdog4: watchdog@424a0000 { compatible = "fsl,imx93-wdt"; reg = <0x424a0000 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG4_GATE>; timeout-sec = <40>; status = "disabled"; }; wdog5: watchdog@424b0000 { compatible = "fsl,imx93-wdt"; reg = <0x424b0000 0x10000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG5_GATE>; timeout-sec = <40>; status = "disabled"; }; tpm3: pwm@424e0000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x424e0000 0x1000>; clocks = <&clk IMX93_CLK_TPM3_GATE>; #pwm-cells = <3>; status = "disabled"; }; tpm4: pwm@424f0000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x424f0000 0x10000>; clocks = <&clk IMX93_CLK_TPM4_GATE>; #pwm-cells = <3>; status = "disabled"; }; tpm5: pwm@42500000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x42500000 0x10000>; clocks = <&clk IMX93_CLK_TPM5_GATE>; #pwm-cells = <3>; status = "disabled"; }; tpm6: pwm@42510000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x42510000 0x10000>; clocks = <&clk IMX93_CLK_TPM6_GATE>; #pwm-cells = <3>; status = "disabled"; }; lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpi2c4: i2c@42540000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42540000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi3: spi@42550000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x42550000 0x10000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi4: spi@42560000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x42560000 0x10000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpuart3: serial@42570000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; status = "disabled"; }; lpuart4: serial@42580000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42580000 0x1000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; status = "disabled"; }; lpuart5: serial@42590000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42590000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; status = "disabled"; }; lpuart6: serial@425a0000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x425a0000 0x1000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; status = "disabled"; }; flexcan2: can@425b0000 { compatible = "fsl,imx93-flexcan"; reg = <0x425b0000 0x10000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_BUS_WAKEUP>, <&clk IMX93_CLK_CAN2_GATE>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX93_CLK_CAN2>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; status = "disabled"; }; flexspi1: spi@425e0000 { compatible = "nxp,imx8mm-fspi"; reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, <&clk IMX93_CLK_FLEXSPI1_GATE>; clock-names = "fspi_en", "fspi"; assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; status = "disabled"; }; lpuart7: serial@42690000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; status = "disabled"; }; lpuart8: serial@426a0000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x426a0000 0x1000>; interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; status = "disabled"; }; lpi2c5: i2c@426b0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426b0000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpi2c6: i2c@426c0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426c0000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpi2c7: i2c@426d0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426d0000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpi2c8: i2c@426e0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426e0000 0x10000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi5: spi@426f0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x426f0000 0x10000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi6: spi@42700000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x42700000 0x10000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi7: spi@42710000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x42710000 0x10000>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; lpspi8: spi@42720000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; reg = <0x42720000 0x10000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; }; aips3: bus@42800000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x42800000 0x800000>; #address-cells = <1>; #size-cells = <1>; ranges; usdhc1: mmc@42850000 { compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x42850000 0x10000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_BUS_WAKEUP>, <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <8>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; status = "disabled"; }; usdhc2: mmc@42860000 { compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x42860000 0x10000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_BUS_WAKEUP>, <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; status = "disabled"; }; fec: ethernet@42890000 { compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x42890000 0x10000>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_ENET1_GATE>, <&clk IMX93_CLK_ENET1_GATE>, <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <100000000>, <250000000>, <50000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; status = "disabled"; }; eqos: ethernet@428a0000 { compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x428a0000 0x10000>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, <&clk IMX93_CLK_ENET_QOS_GATE>, <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>, <&clk IMX93_CLK_ENET_QOS_GATE>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; assigned-clock-rates = <100000000>, <250000000>; intf_mode = <&wakeupmix_gpr 0x28>; snps,clk-csr = <0>; status = "disabled"; }; usdhc3: mmc@428b0000 { compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x428b0000 0x10000>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_BUS_WAKEUP>, <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; status = "disabled"; }; }; gpio2: gpio@43810080 { compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; reg = <0x43810080 0x1000>, <0x43810040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO2_GATE>, <&clk IMX93_CLK_GPIO2_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 4 30>; }; gpio3: gpio@43820080 { compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; reg = <0x43820080 0x1000>, <0x43820040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO3_GATE>, <&clk IMX93_CLK_GPIO3_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; }; gpio4: gpio@43830080 { compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; reg = <0x43830080 0x1000>, <0x43830040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO4_GATE>, <&clk IMX93_CLK_GPIO4_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; }; gpio1: gpio@47400080 { compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; reg = <0x47400080 0x1000>, <0x47400040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO1_GATE>, <&clk IMX93_CLK_GPIO1_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 92 16>; }; ocotp: efuse@47510000 { compatible = "fsl,imx93-ocotp", "syscon"; reg = <0x47510000 0x10000>; #address-cells = <1>; #size-cells = <1>; }; s4muap: mailbox@47520000 { compatible = "fsl,imx93-mu-s4"; reg = <0x47520000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; #mbox-cells = <2>; }; media_blk_ctrl: system-controller@4ac10000 { compatible = "fsl,imx93-media-blk-ctrl", "syscon"; reg = <0x4ac10000 0x10000>; power-domains = <&mediamix>; clocks = <&clk IMX93_CLK_MEDIA_APB>, <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_NIC_MEDIA_GATE>, <&clk IMX93_CLK_MEDIA_DISP_PIX>, <&clk IMX93_CLK_CAM_PIX>, <&clk IMX93_CLK_PXP_GATE>, <&clk IMX93_CLK_LCDIF_GATE>, <&clk IMX93_CLK_ISI_GATE>, <&clk IMX93_CLK_MIPI_CSI_GATE>, <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; #power-domain-cells = <1>; status = "disabled"; }; ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; }; }; }; |