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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include <dt-bindings/clock/k210-clk.h> #include <dt-bindings/pinctrl/k210-fpioa.h> #include <dt-bindings/reset/k210-rst.h> / { /* * Although the K210 is a 64-bit CPU, the address bus is only 32-bits * wide, and the upper half of all addresses is ignored. */ #address-cells = <1>; #size-cells = <1>; compatible = "canaan,kendryte-k210"; aliases { serial0 = &uarths0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; }; /* * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". */ cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; compatible = "canaan,k210", "riscv"; reg = <0>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,none"; i-cache-block-size = <64>; i-cache-size = <0x8000>; d-cache-block-size = <64>; d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "canaan,k210", "riscv"; reg = <1>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,none"; i-cache-block-size = <64>; i-cache-size = <0x8000>; d-cache-block-size = <64>; d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; }; }; }; sram: memory@80000000 { device_type = "memory"; reg = <0x80000000 0x400000>, /* sram0 4 MiB */ <0x80400000 0x200000>, /* sram1 2 MiB */ <0x80600000 0x200000>; /* aisram 2 MiB */ }; sram_controller: memory-controller { compatible = "canaan,k210-sram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, <&sysclk K210_CLK_AI>; clock-names = "sram0", "sram1", "aisram"; }; clocks { in0: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; rom0: nvmem@1000 { reg = <0x1000 0x1000>; read-only; }; clint0: timer@2000000 { compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; #address-cells = <0>; compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu1_intc 11>, <&cpu1_intc 9>; riscv,ndev = <65>; }; uarths0: serial@38000000 { compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; clocks = <&sysclk K210_CLK_CPU>; }; gpio0: gpio-controller@38001000 { #interrupt-cells = <2>; #gpio-cells = <2>; compatible = "canaan,k210-gpiohs", "sifive,gpio0"; reg = <0x38001000 0x1000>; interrupt-controller; interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>, <50>, <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>, <65>; gpio-controller; ngpios = <32>; }; dmac0: dma-controller@50000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>; clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; clock-names = "core-clk", "cfgr-clk"; resets = <&sysrst K210_RST_DMA>; dma-channels = <6>; snps,dma-masters = <2>; snps,priority = <0 1 2 3 4 5>; snps,data-width = <5>; snps,block-size = <0x200000 0x200000 0x200000 0x200000 0x200000 0x200000>; snps,axi-max-burst-len = <256>; }; apb0: bus@50200000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges = <0x50200000 0x50200000 0x200000>; clocks = <&sysclk K210_CLK_APB0>; gpio1: gpio@50200000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0x50200000 0x80>; clocks = <&sysclk K210_CLK_APB0>, <&sysclk K210_CLK_GPIO>; clock-names = "bus", "db"; resets = <&sysrst K210_RST_GPIO>; gpio1_0: gpio-port@0 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "snps,dw-apb-gpio-port"; reg = <0>; interrupt-controller; interrupts = <23>; gpio-controller; ngpios = <8>; }; }; uart1: serial@50210000 { compatible = "snps,dw-apb-uart"; reg = <0x50210000 0x100>; interrupts = <11>; clocks = <&sysclk K210_CLK_UART1>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART1>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; uart2: serial@50220000 { compatible = "snps,dw-apb-uart"; reg = <0x50220000 0x100>; interrupts = <12>; clocks = <&sysclk K210_CLK_UART2>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART2>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; uart3: serial@50230000 { compatible = "snps,dw-apb-uart"; reg = <0x50230000 0x100>; interrupts = <13>; clocks = <&sysclk K210_CLK_UART3>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART3>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; spi2: spi@50240000 { compatible = "canaan,k210-spi"; spi-slave; reg = <0x50240000 0x100>; #address-cells = <0>; #size-cells = <0>; interrupts = <3>; clocks = <&sysclk K210_CLK_SPI2>, <&sysclk K210_CLK_APB0>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI2>; }; i2s0: i2s@50250000 { compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50250000 0x200>; interrupts = <5>; clocks = <&sysclk K210_CLK_I2S0>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S0>; }; i2s1: i2s@50260000 { compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50260000 0x200>; interrupts = <6>; clocks = <&sysclk K210_CLK_I2S1>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S1>; }; i2s2: i2s@50270000 { compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50270000 0x200>; interrupts = <7>; clocks = <&sysclk K210_CLK_I2S2>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S2>; }; i2c0: i2c@50280000 { compatible = "snps,designware-i2c"; reg = <0x50280000 0x100>; interrupts = <8>; clocks = <&sysclk K210_CLK_I2C0>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C0>; }; i2c1: i2c@50290000 { compatible = "snps,designware-i2c"; reg = <0x50290000 0x100>; interrupts = <9>; clocks = <&sysclk K210_CLK_I2C1>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C1>; }; i2c2: i2c@502a0000 { compatible = "snps,designware-i2c"; reg = <0x502A0000 0x100>; interrupts = <10>; clocks = <&sysclk K210_CLK_I2C2>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C2>; }; fpioa: pinmux@502b0000 { compatible = "canaan,k210-fpioa"; reg = <0x502B0000 0x100>; clocks = <&sysclk K210_CLK_FPIOA>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_FPIOA>; canaan,k210-sysctl-power = <&sysctl 108>; }; timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; reg = <0x502D0000 0x14>; interrupts = <14>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER0>; }; timer1: timer@502d0014 { compatible = "snps,dw-apb-timer"; reg = <0x502D0014 0x14>; interrupts = <15>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER0>; }; timer2: timer@502e0000 { compatible = "snps,dw-apb-timer"; reg = <0x502E0000 0x14>; interrupts = <16>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER1>; }; timer3: timer@502e0014 { compatible = "snps,dw-apb-timer"; reg = <0x502E0014 0x114>; interrupts = <17>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER1>; }; timer4: timer@502f0000 { compatible = "snps,dw-apb-timer"; reg = <0x502F0000 0x14>; interrupts = <18>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER2>; }; timer5: timer@502f0014 { compatible = "snps,dw-apb-timer"; reg = <0x502F0014 0x14>; interrupts = <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER2>; }; }; apb1: bus@50400000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges = <0x50400000 0x50400000 0x40100>; clocks = <&sysclk K210_CLK_APB1>; wdt0: watchdog@50400000 { compatible = "snps,dw-wdt"; reg = <0x50400000 0x100>; interrupts = <21>; clocks = <&sysclk K210_CLK_WDT0>, <&sysclk K210_CLK_APB1>; clock-names = "tclk", "pclk"; resets = <&sysrst K210_RST_WDT0>; }; wdt1: watchdog@50410000 { compatible = "snps,dw-wdt"; reg = <0x50410000 0x100>; interrupts = <22>; clocks = <&sysclk K210_CLK_WDT1>, <&sysclk K210_CLK_APB1>; clock-names = "tclk", "pclk"; resets = <&sysrst K210_RST_WDT1>; }; sysctl: syscon@50440000 { compatible = "canaan,k210-sysctl", "syscon", "simple-mfd"; reg = <0x50440000 0x100>; clocks = <&sysclk K210_CLK_APB1>; clock-names = "pclk"; sysclk: clock-controller { #clock-cells = <1>; compatible = "canaan,k210-clk"; clocks = <&in0>; }; sysrst: reset-controller { compatible = "canaan,k210-rst"; #reset-cells = <1>; }; reboot: syscon-reboot { compatible = "syscon-reboot"; regmap = <&sysctl>; offset = <48>; mask = <1>; value = <1>; }; }; }; apb2: bus@52000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges = <0x52000000 0x52000000 0x2000200>; clocks = <&sysclk K210_CLK_APB2>; spi0: spi@52000000 { #address-cells = <1>; #size-cells = <0>; compatible = "canaan,k210-spi"; reg = <0x52000000 0x100>; interrupts = <1>; clocks = <&sysclk K210_CLK_SPI0>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI0>; reset-names = "spi"; num-cs = <4>; reg-io-width = <4>; }; spi1: spi@53000000 { #address-cells = <1>; #size-cells = <0>; compatible = "canaan,k210-spi"; reg = <0x53000000 0x100>; interrupts = <2>; clocks = <&sysclk K210_CLK_SPI1>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI1>; reset-names = "spi"; num-cs = <4>; reg-io-width = <4>; }; spi3: spi@54000000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwc-ssi-1.01a"; reg = <0x54000000 0x200>; interrupts = <4>; clocks = <&sysclk K210_CLK_SPI3>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI3>; reset-names = "spi"; num-cs = <4>; reg-io-width = <4>; }; }; }; }; |