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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef R819XUSB_CMDPKT_H #define R819XUSB_CMDPKT_H /* Different command packet have dedicated message length and definition. */ #define CMPK_RX_TX_FB_SIZE sizeof(struct cmd_pkt_tx_feedback) /* 20 */ #define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(struct cmd_pkt_set_configuration) /* 16 */ #define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t) #define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t) /* 2008/05/08 amy For USB constant. */ #define ISR_TX_BCN_OK BIT(27) /* Transmit Beacon OK */ #define ISR_TX_BCN_ERR BIT(26) /* Transmit Beacon Error */ #define ISR_BCN_TIMER_INTR BIT(13) /* Beacon Timer Interrupt */ /* Define element ID of command packet. */ /*------------------------------Define structure----------------------------*/ /* Define different command packet structure. */ /* 1. RX side: TX feedback packet. */ struct cmd_pkt_tx_feedback { /* DWORD 0 */ u8 element_id; /* Command packet type. */ u8 length; /* Command packet length. */ /* Change tx feedback info field. */ /*------TX Feedback Info Field */ u8 TID:4; u8 fail_reason:3; u8 tok:1; /* Transmit ok. */ u8 reserve1:4; u8 pkt_type:2; u8 bandwidth:1; u8 qos_pkt:1; /* DWORD 1 */ u8 reserve2; /*------TX Feedback Info Field */ u8 retry_cnt; u16 pkt_id; /* DWORD 3 */ u16 seq_num; u8 s_rate; /* Start rate. */ u8 f_rate; /* Final rate. */ /* DWORD 4 */ u8 s_rts_rate; u8 f_rts_rate; u16 pkt_length; /* DWORD 5 */ u16 reserve3; u16 duration; }; /* 2. RX side: Interrupt status packet. It includes Beacon State, * Beacon Timer Interrupt and other useful information in MAC ISR Reg. */ struct cmd_pkt_interrupt_status { u8 element_id; /* Command packet type. */ u8 length; /* Command packet length. */ u16 reserve; u32 interrupt_status; /* Interrupt Status. */ }; /* 3. TX side: Set configuration packet. */ struct cmd_pkt_set_configuration { u8 element_id; /* Command packet type. */ u8 length; /* Command packet length. */ u16 reserve1; /* Configuration info. */ u8 cfg_reserve1:3; u8 cfg_size:2; u8 cfg_type:2; u8 cfg_action:1; u8 cfg_reserve2; u8 cfg_page:4; u8 cfg_reserve3:4; u8 cfg_offset; u32 value; u32 mask; }; /* 4. Both side : TX/RX query configuration packet. The query structure is the * same as set configuration. */ #define cmpk_query_cfg cmd_pkt_set_configuration /* 5. Multi packet feedback status. */ typedef struct tag_tx_stats_feedback { /* For endian transfer --> Driver will not the same as * firmware structure. */ /* DW 0 */ u16 reserve1; u8 length; /* Command packet length */ u8 element_id; /* Command packet type */ /* DW 1 */ u16 txfail; /* Tx fail count */ u16 txok; /* Tx ok count */ /* DW 2 */ u16 txmcok; /* Tx multicast */ u16 txretry; /* Tx retry count */ /* DW 3 */ u16 txucok; /* Tx unicast */ u16 txbcok; /* Tx broadcast */ /* DW 4 */ u16 txbcfail; u16 txmcfail; /* DW 5 */ u16 reserve2; u16 txucfail; /* DW 6-8 */ u32 txmclength; u32 txbclength; u32 txuclength; /* DW 9 */ u16 reserve3_23; u8 reserve3_1; u8 rate; } __packed cmpk_tx_status_t; /* 6. Debug feedback message. */ /* Define RX debug message */ typedef struct tag_rx_debug_message_feedback { /* For endian transfer --> for driver */ /* DW 0 */ u16 reserve1; u8 length; /* Command packet length */ u8 element_id; /* Command packet type */ /* DW 1-?? */ /* Variable debug message. */ } cmpk_rx_dbginfo_t; /* Define transmit rate history. For big endian format. */ typedef struct tag_tx_rate_history { /* For endian transfer --> for driver */ /* DW 0 */ u8 element_id; /* Command packet type */ u8 length; /* Command packet length */ u16 reserved1; /* DW 1-2 CCK rate counter */ u16 cck[4]; /* DW 3-6 */ u16 ofdm[8]; /* DW 7-14 BW=0 SG=0 * DW 15-22 BW=1 SG=0 * DW 23-30 BW=0 SG=1 * DW 31-38 BW=1 SG=1 */ u16 ht_mcs[4][16]; } __packed cmpk_tx_rahis_t; typedef enum tag_command_packet_directories { RX_TX_FEEDBACK = 0, RX_INTERRUPT_STATUS = 1, TX_SET_CONFIG = 2, BOTH_QUERY_CONFIG = 3, RX_TX_STATUS = 4, RX_DBGINFO_FEEDBACK = 5, RX_TX_PER_PKT_FEEDBACK = 6, RX_TX_RATE_HISTORY = 7, RX_CMD_ELE_MAX } cmpk_element_e; typedef enum _rt_status { RT_STATUS_SUCCESS, RT_STATUS_FAILURE, RT_STATUS_PENDING, RT_STATUS_RESOURCE } rt_status, *prt_status; u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats *pstats); rt_status SendTxCommandPacket(struct net_device *dev, void *pData, u32 DataLen); #endif |