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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 | /* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "hw_translate_dcn315.h" #include "dm_services.h" #include "include/gpio_types.h" #include "../hw_translate.h" #include "dcn/dcn_3_1_5_offset.h" #include "dcn/dcn_3_1_5_sh_mask.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ #define DCN_BASE__INST0_SEG0 0x00000012 #define DCN_BASE__INST0_SEG1 0x000000C0 #define DCN_BASE__INST0_SEG2 0x000034C0 #define DCN_BASE__INST0_SEG3 0x00009000 #define DCN_BASE__INST0_SEG4 0x02403C00 #define DCN_BASE__INST0_SEG5 0 /* DCN */ #define block HPD #define reg_num 0 #undef BASE_INNER #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg #define BASE(seg) BASE_INNER(seg) #undef REG #define REG(reg_name)\ BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name #define SF_HPD(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix /* macros to expend register list macro defined in HW object header file * end *********************/ static bool offset_to_id( uint32_t offset, uint32_t mask, enum gpio_id *id, uint32_t *en) { switch (offset) { /* GENERIC */ case REG(DC_GPIO_GENERIC_A): *id = GPIO_ID_GENERIC; switch (mask) { case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: *en = GPIO_GENERIC_A; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: *en = GPIO_GENERIC_B; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: *en = GPIO_GENERIC_C; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: *en = GPIO_GENERIC_D; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: *en = GPIO_GENERIC_E; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: *en = GPIO_GENERIC_F; return true; case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: *en = GPIO_GENERIC_G; return true; default: ASSERT_CRITICAL(false); return false; } break; /* HPD */ case REG(DC_GPIO_HPD_A): *id = GPIO_ID_HPD; switch (mask) { case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: *en = GPIO_HPD_1; return true; case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: *en = GPIO_HPD_2; return true; case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: *en = GPIO_HPD_3; return true; case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: *en = GPIO_HPD_4; return true; case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: *en = GPIO_HPD_5; return true; case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: *en = GPIO_HPD_6; return true; default: ASSERT_CRITICAL(false); return false; } break; /* REG(DC_GPIO_GENLK_MASK */ case REG(DC_GPIO_GENLK_A): *id = GPIO_ID_GSL; switch (mask) { case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: *en = GPIO_GSL_GENLOCK_CLOCK; return true; case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: *en = GPIO_GSL_GENLOCK_VSYNC; return true; case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: *en = GPIO_GSL_SWAPLOCK_A; return true; case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: *en = GPIO_GSL_SWAPLOCK_B; return true; default: ASSERT_CRITICAL(false); return false; } break; /* DDC */ /* we don't care about the GPIO_ID for DDC * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK * directly in the create method */ case REG(DC_GPIO_DDC1_A): *en = GPIO_DDC_LINE_DDC1; return true; case REG(DC_GPIO_DDC2_A): *en = GPIO_DDC_LINE_DDC2; return true; case REG(DC_GPIO_DDC3_A): *en = GPIO_DDC_LINE_DDC3; return true; case REG(DC_GPIO_DDC4_A): *en = GPIO_DDC_LINE_DDC4; return true; case REG(DC_GPIO_DDC5_A): *en = GPIO_DDC_LINE_DDC5; return true; case REG(DC_GPIO_DDCVGA_A): *en = GPIO_DDC_LINE_DDC_VGA; return true; /* * case REG(DC_GPIO_I2CPAD_A): not exit * case REG(DC_GPIO_PWRSEQ_A): * case REG(DC_GPIO_PAD_STRENGTH_1): * case REG(DC_GPIO_PAD_STRENGTH_2): * case REG(DC_GPIO_DEBUG): */ /* UNEXPECTED */ default: /* case REG(DC_GPIO_SYNCA_A): not exist */ ASSERT_CRITICAL(false); return false; } } static bool id_to_offset( enum gpio_id id, uint32_t en, struct gpio_pin_info *info) { bool result = true; switch (id) { case GPIO_ID_DDC_DATA: info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK; switch (en) { case GPIO_DDC_LINE_DDC1: info->offset = REG(DC_GPIO_DDC1_A); break; case GPIO_DDC_LINE_DDC2: info->offset = REG(DC_GPIO_DDC2_A); break; case GPIO_DDC_LINE_DDC3: info->offset = REG(DC_GPIO_DDC3_A); break; case GPIO_DDC_LINE_DDC4: info->offset = REG(DC_GPIO_DDC4_A); break; case GPIO_DDC_LINE_DDC5: info->offset = REG(DC_GPIO_DDC5_A); break; case GPIO_DDC_LINE_DDC_VGA: info->offset = REG(DC_GPIO_DDCVGA_A); break; case GPIO_DDC_LINE_I2C_PAD: default: ASSERT_CRITICAL(false); result = false; } break; case GPIO_ID_DDC_CLOCK: info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK; switch (en) { case GPIO_DDC_LINE_DDC1: info->offset = REG(DC_GPIO_DDC1_A); break; case GPIO_DDC_LINE_DDC2: info->offset = REG(DC_GPIO_DDC2_A); break; case GPIO_DDC_LINE_DDC3: info->offset = REG(DC_GPIO_DDC3_A); break; case GPIO_DDC_LINE_DDC4: info->offset = REG(DC_GPIO_DDC4_A); break; case GPIO_DDC_LINE_DDC5: info->offset = REG(DC_GPIO_DDC5_A); break; case GPIO_DDC_LINE_DDC_VGA: info->offset = REG(DC_GPIO_DDCVGA_A); break; case GPIO_DDC_LINE_I2C_PAD: default: ASSERT_CRITICAL(false); result = false; } break; case GPIO_ID_GENERIC: info->offset = REG(DC_GPIO_GENERIC_A); switch (en) { case GPIO_GENERIC_A: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; break; case GPIO_GENERIC_B: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; break; case GPIO_GENERIC_C: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; break; case GPIO_GENERIC_D: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; break; case GPIO_GENERIC_E: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; break; case GPIO_GENERIC_F: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; break; case GPIO_GENERIC_G: info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; break; default: ASSERT_CRITICAL(false); result = false; } break; case GPIO_ID_HPD: info->offset = REG(DC_GPIO_HPD_A); switch (en) { case GPIO_HPD_1: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; break; case GPIO_HPD_2: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; break; case GPIO_HPD_3: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; break; case GPIO_HPD_4: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; break; case GPIO_HPD_5: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; break; case GPIO_HPD_6: info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; break; default: ASSERT_CRITICAL(false); result = false; } break; case GPIO_ID_GSL: switch (en) { case GPIO_GSL_GENLOCK_CLOCK: /*not implmented*/ ASSERT_CRITICAL(false); result = false; break; case GPIO_GSL_GENLOCK_VSYNC: /*not implmented*/ ASSERT_CRITICAL(false); result = false; break; case GPIO_GSL_SWAPLOCK_A: /*not implmented*/ ASSERT_CRITICAL(false); result = false; break; case GPIO_GSL_SWAPLOCK_B: /*not implmented*/ ASSERT_CRITICAL(false); result = false; break; default: ASSERT_CRITICAL(false); result = false; } break; case GPIO_ID_SYNC: case GPIO_ID_VIP_PAD: default: ASSERT_CRITICAL(false); result = false; } if (result) { info->offset_y = info->offset + 2; info->offset_en = info->offset + 1; info->offset_mask = info->offset - 1; info->mask_y = info->mask; info->mask_en = info->mask; info->mask_mask = info->mask; } return result; } /* function table */ static const struct hw_translate_funcs funcs = { .offset_to_id = offset_to_id, .id_to_offset = id_to_offset, }; /* * dal_hw_translate_dcn30_init * * @brief * Initialize Hw translate function pointers. * * @param * struct hw_translate *tr - [out] struct of function pointers * */ void dal_hw_translate_dcn315_init(struct hw_translate *tr) { tr->funcs = &funcs; } |