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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Socionext UniPhier USB3 High-Speed (HS) PHY description: | This describes the devicetree bindings for PHY interfaces built into USB3 controller implemented on Socionext UniPhier SoCs. Although the controller includes High-Speed PHY and Super-Speed PHY, this describes about High-Speed PHY. maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> properties: compatible: enum: - socionext,uniphier-pro5-usb3-hsphy - socionext,uniphier-pxs2-usb3-hsphy - socionext,uniphier-ld20-usb3-hsphy - socionext,uniphier-pxs3-usb3-hsphy - socionext,uniphier-nx1-usb3-hsphy reg: maxItems: 1 "#phy-cells": const: 0 clocks: minItems: 2 maxItems: 3 clock-names: true resets: maxItems: 2 reset-names: true vbus-supply: description: A phandle to the regulator for USB VBUS nvmem-cells: maxItems: 3 description: Phandles to nvmem cell that contains the trimming data. Available only for HS-PHY implemented on LD20 and PXs3, and if unspecified, default value is used. nvmem-cell-names: items: - const: rterm - const: sel_t - const: hs_i description: Should be the following names, which correspond to each nvmem-cells. All of the 3 parameters associated with the above names are required for each port, if any one is omitted, the trimming data of the port will not be set at all. allOf: - if: properties: compatible: contains: const: socionext,uniphier-pro5-usb3-hsphy then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: gio - const: link resets: minItems: 2 maxItems: 2 reset-names: items: - const: gio - const: link - if: properties: compatible: contains: enum: - socionext,uniphier-pxs2-usb3-hsphy - socionext,uniphier-ld20-usb3-hsphy then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: link - const: phy resets: minItems: 2 maxItems: 2 reset-names: items: - const: link - const: phy - if: properties: compatible: contains: enum: - socionext,uniphier-pxs3-usb3-hsphy - socionext,uniphier-nx1-usb3-hsphy then: properties: clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 items: - const: link - const: phy - const: phy-ext resets: minItems: 2 maxItems: 2 reset-names: items: - const: link - const: phy required: - compatible - reg - "#phy-cells" - clocks - clock-names - resets - reset-names additionalProperties: false examples: - | usb_hsphy0: phy@200 { compatible = "socionext,uniphier-ld20-usb3-hsphy"; reg = <0x200 0x10>; #phy-cells = <0>; clock-names = "link", "phy"; clocks = <&sys_clk 14>, <&sys_clk 16>; reset-names = "link", "phy"; resets = <&sys_rst 14>, <&sys_rst 16>; vbus-supply = <&usb_vbus0>; nvmem-cell-names = "rterm", "sel_t", "hs_i"; nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; }; |