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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright 2023 Realtek Semiconductor Corporation %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek DHC SoCs USB 2.0 PHY maintainers: - Stanley Chang <stanley_chang@realtek.com> description: | Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs. The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs support multiple XHCI controllers. One PHY device node maps to one XHCI controller. RTD1295/RTD1619 SoCs USB The USB architecture includes three XHCI controllers. Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some controllers. XHCI controller#0 -- usb2phy -- phy#0 |- usb3phy -- phy#0 XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 |- usb3phy -- phy#0 RTD1395 SoCs USB The USB architecture includes two XHCI controllers. The controller#0 has one USB 2.0 PHY. The controller#1 includes two USB 2.0 PHY. XHCI controller#0 -- usb2phy -- phy#0 XHCI controller#1 -- usb2phy -- phy#0 |- phy#1 RTD1319/RTD1619b SoCs USB The USB architecture includes three XHCI controllers. Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2. XHCI controller#0 -- usb2phy -- phy#0 XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 |- usb3phy -- phy#0 RTD1319d SoCs USB The USB architecture includes three XHCI controllers. Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0. XHCI controller#0 -- usb2phy -- phy#0 |- usb3phy -- phy#0 XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 RTD1312c/RTD1315e SoCs USB The USB architecture includes three XHCI controllers. Each XHCI maps to one USB 2.0 PHY. XHCI controller#0 -- usb2phy -- phy#0 XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 properties: compatible: enum: - realtek,rtd1295-usb2phy - realtek,rtd1312c-usb2phy - realtek,rtd1315e-usb2phy - realtek,rtd1319-usb2phy - realtek,rtd1319d-usb2phy - realtek,rtd1395-usb2phy - realtek,rtd1395-usb2phy-2port - realtek,rtd1619-usb2phy - realtek,rtd1619b-usb2phy reg: items: - description: PHY data registers - description: PHY control registers "#phy-cells": const: 0 nvmem-cells: maxItems: 2 description: Phandles to nvmem cell that contains the trimming data. If unspecified, default value is used. nvmem-cell-names: items: - const: usb-dc-cal - const: usb-dc-dis description: The following names, which correspond to each nvmem-cells. usb-dc-cal is the driving level for each phy specified via efuse. usb-dc-dis is the disconnection level for each phy specified via efuse. realtek,inverse-hstx-sync-clock: description: For one of the phys of RTD1619b SoC, the synchronous clock of the high-speed tx must be inverted. type: boolean realtek,driving-level: description: Control the magnitude of High speed Dp/Dm output swing (mV). For a different board or port, the original magnitude maybe not meet the specification. In this situation we can adjust the value to meet the specification. $ref: /schemas/types.yaml#/definitions/uint32 default: 8 minimum: 0 maximum: 31 realtek,driving-level-compensate: description: For RTD1315e SoC, the driving level can be adjusted by reading the efuse table. This property provides drive compensation. If the magnitude of High speed Dp/Dm output swing still not meet the specification, then we can set this value to meet the specification. $ref: /schemas/types.yaml#/definitions/int32 default: 0 minimum: -8 maximum: 8 realtek,disconnection-compensate: description: This adjusts the disconnection level compensation for the different boards with different disconnection level. $ref: /schemas/types.yaml#/definitions/int32 default: 0 minimum: -8 maximum: 8 required: - compatible - reg - "#phy-cells" allOf: - if: not: properties: compatible: contains: enum: - realtek,rtd1619b-usb2phy then: properties: realtek,inverse-hstx-sync-clock: false - if: not: properties: compatible: contains: enum: - realtek,rtd1315e-usb2phy then: properties: realtek,driving-level-compensate: false additionalProperties: false examples: - | usb-phy@13214 { compatible = "realtek,rtd1619b-usb2phy"; reg = <0x13214 0x4>, <0x28280 0x4>; #phy-cells = <0>; nvmem-cells = <&otp_usb_port0_dc_cal>, <&otp_usb_port0_dc_dis>; nvmem-cell-names = "usb-dc-cal", "usb-dc-dis"; realtek,inverse-hstx-sync-clock; realtek,driving-level = <0xa>; realtek,disconnection-compensate = <(-1)>; }; |