Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm QMP PHY controller (PCIe, SC8280XP) maintainers: - Vinod Koul <vkoul@kernel.org> description: The QMP PHY controller supports physical layer functionality for a number of controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. properties: compatible: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx65-qmp-gen4x2-pcie-phy - qcom,sm8150-qmp-gen3x1-pcie-phy - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy reg: minItems: 1 maxItems: 2 clocks: minItems: 5 maxItems: 7 clock-names: minItems: 5 items: - const: aux - const: cfg_ahb - const: ref - enum: [rchng, refgen] - const: pipe - const: pipediv2 - const: phy_aux power-domains: maxItems: 1 resets: minItems: 1 maxItems: 2 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr vdda-phy-supply: true vdda-pll-supply: true vdda-qref-supply: true qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle of TCSR syscon - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY "#clock-cells": const: 0 clock-output-names: maxItems: 1 "#phy-cells": const: 0 required: - compatible - reg - clocks - clock-names - resets - reset-names - vdda-phy-supply - vdda-pll-supply - "#clock-cells" - clock-output-names - "#phy-cells" additionalProperties: false allOf: - if: properties: compatible: contains: enum: - qcom,sc8280xp-qmp-gen3x4-pcie-phy then: properties: reg: items: - description: port a - description: port b required: - qcom,4ln-config-sel else: properties: reg: maxItems: 1 - if: properties: compatible: contains: enum: - qcom,sc8180x-qmp-pcie-phy - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy - qcom,sm8150-qmp-gen3x1-pcie-phy - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy then: properties: clocks: maxItems: 5 clock-names: maxItems: 5 - if: properties: compatible: contains: enum: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy then: properties: clocks: minItems: 6 clock-names: minItems: 6 - if: properties: compatible: contains: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy then: properties: clocks: minItems: 7 clock-names: minItems: 7 - if: properties: compatible: contains: enum: - qcom,sm8550-qmp-gen4x2-pcie-phy then: properties: resets: minItems: 2 reset-names: minItems: 2 else: properties: resets: maxItems: 1 reset-names: maxItems: 1 examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> pcie2b_phy: phy@1c18000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x01c18000 0x2000>; clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2B_GDSC>; resets = <&gcc GCC_PCIE_2B_PHY_BCR>; reset-names = "phy"; vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; #clock-cells = <0>; clock-output-names = "pcie_2b_pipe_clk"; #phy-cells = <0>; }; pcie2a_phy: phy@1c24000 { compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2A_GDSC>; resets = <&gcc GCC_PCIE_2A_PHY_BCR>; reset-names = "phy"; vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; qcom,4ln-config-sel = <&tcsr 0xa044 0>; #clock-cells = <0>; clock-output-names = "pcie_2a_pipe_clk"; #phy-cells = <0>; }; |