Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 USB HS PHY controller description: The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI switch. It controls PHY configuration and status, and the UTMI+ switch that selects either OTG or HOST controller for the second PHY port. It also sets PLL configuration. USBPHYC |_ PLL | |_ PHY port#1 _________________ HOST controller | __ | | / 1|________________| |_ PHY port#2 ----| |________________ | \_0| | |_ UTMI switch_______| OTG controller maintainers: - Amelie Delaunay <amelie.delaunay@foss.st.com> properties: compatible: const: st,stm32mp1-usbphyc reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 "#address-cells": const: 1 "#size-cells": const: 0 vdda1v1-supply: description: regulator providing 1V1 power supply to the PLL block vdda1v8-supply: description: regulator providing 1V8 power supply to the PLL block '#clock-cells': description: number of clock cells for ck_usbo_48m consumer const: 0 # Required child nodes: patternProperties: "^usb-phy@[0|1]$": type: object description: Each port the controller provides must be represented as a sub-node. properties: reg: description: phy port index. maxItems: 1 phy-supply: description: regulator providing 3V3 power supply to the PHY. "#phy-cells": enum: [ 0x0, 0x1 ] connector: type: object $ref: /schemas/connector/usb-connector.yaml unevaluatedProperties: false properties: vbus-supply: true # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due # to USB connector/receptacle, routing, ESD protection component,... Here is the list of # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- # Speed, LS for Low-Speed) st,current-boost-microamp: description: Current boosting in uA enum: [ 1000, 2000 ] st,no-lsfs-fb-cap: description: Disables the LS/FS feedback capacitor type: boolean st,decrease-hs-slew-rate: description: Decreases the HS driver slew rate by 10% type: boolean st,tune-hs-dc-level: description: | Tunes the HS driver DC level - <0> normal level - <1> increases the level by 5 to 7 mV - <2> increases the level by 10 to 14 mV - <3> decreases the level by 5 to 7 mV $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 0 st,enable-fs-rftime-tuning: description: Enables the FS rise/fall tuning option type: boolean st,enable-hs-rftime-reduction: description: Enables the HS rise/fall reduction feature type: boolean st,trim-hs-current: description: | Controls HS driver current trimming for choke compensation - <0> = 18.87 mA target current / nominal + 0% - <1> = 19.165 mA target current / nominal + 1.56% - <2> = 19.46 mA target current / nominal + 3.12% - <3> = 19.755 mA target current / nominal + 4.68% - <4> = 20.05 mA target current / nominal + 6.24% - <5> = 20.345 mA target current / nominal + 7.8% - <6> = 20.64 mA target current / nominal + 9.36% - <7> = 20.935 mA target current / nominal + 10.92% - <8> = 21.23 mA target current / nominal + 12.48% - <9> = 21.525 mA target current / nominal + 14.04% - <10> = 21.82 mA target current / nominal + 15.6% - <11> = 22.115 mA target current / nominal + 17.16% - <12> = 22.458 mA target current / nominal + 19.01% - <13> = 22.755 mA target current / nominal + 20.58% - <14> = 23.052 mA target current / nominal + 22.16% - <15> = 23.348 mA target current / nominal + 23.73% $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 15 default: 0 st,trim-hs-impedance: description: | Controls HS driver impedance tuning for choke compensation - <0> = no impedance offset - <1> = reduce the impedance by 2 ohms - <2> = reduce the impedance by 4 ohms - <3> = reduce the impedance by 6 ohms $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 0 st,tune-squelch-level: description: | Tunes the squelch DC threshold value - <0> = no shift in threshold - <1> = threshold shift by +7 mV - <2> = threshold shift by -5 mV - <3> = threshold shift by +14 mV $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 0 st,enable-hs-rx-gain-eq: description: Enables the HS Rx gain equalizer type: boolean st,tune-hs-rx-offset: description: | Adjusts the HS Rx offset - <0> = no offset - <1> = offset of +5 mV - <2> = offset of +10 mV - <3> = offset of -5 mV $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 0 st,no-hs-ftime-ctrl: description: Disables the HS fall time control of single ended signals during pre-emphasis type: boolean st,no-lsfs-sc: description: Disables the short circuit protection in LS/FS driver type: boolean st,enable-hs-tx-staggering: description: Enables the basic staggering in HS Tx mode type: boolean allOf: - if: properties: reg: const: 0 then: properties: "#phy-cells": const: 0 else: properties: "#phy-cells": const: 1 description: The value is used to select UTMI switch output. 0 for OTG controller and 1 for Host controller. required: - reg - phy-supply - "#phy-cells" additionalProperties: false required: - compatible - reg - clocks - "#address-cells" - "#size-cells" - vdda1v1-supply - vdda1v8-supply - usb-phy@0 - usb-phy@1 additionalProperties: false examples: - | #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/reset/stm32mp1-resets.h> usbphyc: usbphyc@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; vdda1v1-supply = <®11>; vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; st,tune-hs-dc-level = <2>; st,enable-fs-rftime-tuning; st,enable-hs-rftime-reduction; st,trim-hs-current = <15>; st,trim-hs-impedance = <1>; st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; }; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; #phy-cells = <1>; st,tune-hs-dc-level = <2>; st,enable-fs-rftime-tuning; st,enable-hs-rftime-reduction; st,trim-hs-current = <15>; st,trim-hs-impedance = <1>; st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; }; }; ... |