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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra USB PHY maintainers: - Dmitry Osipenko <digetx@gmail.com> - Jon Hunter <jonathanh@nvidia.com> - Thierry Reding <thierry.reding@gmail.com> properties: compatible: oneOf: - items: - enum: - nvidia,tegra124-usb-phy - nvidia,tegra114-usb-phy - enum: - nvidia,tegra30-usb-phy - items: - enum: - nvidia,tegra30-usb-phy - nvidia,tegra20-usb-phy reg: minItems: 1 maxItems: 2 description: | PHY0 and PHY2 share power and ground, PHY0 contains shared registers. PHY0 and PHY2 must specify two register sets, where the first set is PHY own registers and the second set is the PHY0 registers. clocks: anyOf: - items: - description: Registers clock - description: Main PHY clock - items: - description: Registers clock - description: Main PHY clock - description: ULPI PHY clock - items: - description: Registers clock - description: Main PHY clock - description: UTMI pads control registers clock - items: - description: Registers clock - description: Main PHY clock - description: UTMI timeout clock - description: UTMI pads control registers clock clock-names: oneOf: - items: - const: reg - const: pll_u - items: - const: reg - const: pll_u - const: ulpi-link - items: - const: reg - const: pll_u - const: utmi-pads - items: - const: reg - const: pll_u - const: timer - const: utmi-pads interrupts: maxItems: 1 resets: oneOf: - maxItems: 1 description: PHY reset - items: - description: PHY reset - description: UTMI pads reset reset-names: oneOf: - const: usb - items: - const: usb - const: utmi-pads "#phy-cells": const: 0 phy_type: $ref: /schemas/types.yaml#/definitions/string enum: [utmi, ulpi, hsic] dr_mode: $ref: /schemas/types.yaml#/definitions/string enum: [host, peripheral, otg] default: host vbus-supply: description: Regulator controlling USB VBUS. nvidia,has-legacy-mode: description: | Indicates whether this controller can operate in legacy mode (as APX 2500 / 2600). In legacy mode some registers are accessed through the APB_MISC base address instead of the USB controller. type: boolean nvidia,is-wired: description: | Indicates whether we can do certain kind of power optimizations for the devices that are always connected. e.g. modem. type: boolean nvidia,has-utmi-pad-registers: description: | Indicates whether this controller contains the UTMI pad control registers common to all USB controllers. type: boolean nvidia,hssync-start-delay: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 31 description: | Number of 480 MHz clock cycles to wait before start of sync launches RxActive. nvidia,elastic-limit: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 31 description: Variable FIFO Depth of elastic input store. nvidia,idle-wait-delay: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 31 description: | Number of 480 MHz clock cycles of idle to wait before declare IDLE. nvidia,term-range-adj: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 15 description: Range adjustment on terminations. nvidia,xcvr-setup: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 127 description: Input of XCVR cell, HS driver output control. nvidia,xcvr-setup-use-fuses: description: Indicates that the value is read from the on-chip fuses. type: boolean nvidia,xcvr-lsfslew: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 description: LS falling slew rate control. nvidia,xcvr-lsrslew: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 description: LS rising slew rate control. nvidia,xcvr-hsslew: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 511 description: HS slew rate control. nvidia,hssquelch-level: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 description: HS squelch detector level. nvidia,hsdiscon-level: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 7 description: HS disconnect detector level. nvidia,phy-reset-gpio: maxItems: 1 description: GPIO used to reset the PHY. nvidia,pmc: $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: Phandle to Power Management controller. - description: USB controller ID. description: Phandle to Power Management controller. required: - compatible - reg - clocks - clock-names - resets - reset-names - "#phy-cells" - phy_type additionalProperties: false allOf: - if: properties: phy_type: const: utmi then: properties: reg: minItems: 2 maxItems: 2 resets: maxItems: 2 reset-names: maxItems: 2 required: - nvidia,hssync-start-delay - nvidia,elastic-limit - nvidia,idle-wait-delay - nvidia,term-range-adj - nvidia,xcvr-lsfslew - nvidia,xcvr-lsrslew anyOf: - required: ["nvidia,xcvr-setup"] - required: ["nvidia,xcvr-setup-use-fuses"] if: properties: compatible: contains: const: nvidia,tegra30-usb-phy then: properties: clocks: maxItems: 3 clock-names: items: - const: reg - const: pll_u - const: utmi-pads required: - nvidia,xcvr-hsslew - nvidia,hssquelch-level - nvidia,hsdiscon-level else: properties: clocks: maxItems: 4 clock-names: items: - const: reg - const: pll_u - const: timer - const: utmi-pads - if: properties: phy_type: const: ulpi then: properties: reg: minItems: 1 maxItems: 1 clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 maxItems: 3 oneOf: - items: - const: reg - const: pll_u - items: - const: reg - const: pll_u - const: ulpi-link resets: minItems: 1 maxItems: 2 reset-names: minItems: 1 maxItems: 2 examples: - | #include <dt-bindings/clock/tegra124-car.h> usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; interrupts = <0 97 4>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, <&tegra_car TEGRA124_CLK_USBD>; clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; nvidia,term-range-adj = <6>; nvidia,xcvr-setup = <9>; nvidia,xcvr-lsfslew = <0>; nvidia,xcvr-lsrslew = <3>; nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,pmc = <&tegra_pmc 2>; }; - | #include <dt-bindings/clock/tegra20-car.h> usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; interrupts = <0 21 4>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, <&tegra_car TEGRA20_CLK_CDEV2>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; nvidia,pmc = <&tegra_pmc 1>; }; |