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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Lantiq VRX200 and ARX300 PCIe PHY maintainers: - Martin Blumenstingl <martin.blumenstingl@googlemail.com> properties: "#phy-cells": const: 1 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h> compatible: enum: - lantiq,vrx200-pcie-phy - lantiq,arx300-pcie-phy reg: maxItems: 1 clocks: items: - description: PHY module clock - description: PDI register clock clock-names: items: - const: phy - const: pdi resets: items: - description: exclusive PHY reset line - description: shared reset line between the PCIe PHY and PCIe controller reset-names: items: - const: phy - const: pcie lantiq,rcu: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the RCU syscon lantiq,rcu-endian-offset: $ref: /schemas/types.yaml#/definitions/uint32 description: the offset of the endian registers for this PHY instance in the RCU syscon lantiq,rcu-big-endian-mask: $ref: /schemas/types.yaml#/definitions/uint32 description: the mask to set the PDI (PHY) registers for this PHY instance to big endian big-endian: description: Configures the PDI (PHY) registers in big-endian mode type: boolean little-endian: description: Configures the PDI (PHY) registers in big-endian mode type: boolean required: - "#phy-cells" - compatible - reg - clocks - clock-names - resets - reset-names - lantiq,rcu - lantiq,rcu-endian-offset - lantiq,rcu-big-endian-mask additionalProperties: false examples: - | pcie0_phy: phy@106800 { compatible = "lantiq,vrx200-pcie-phy"; reg = <0x106800 0x100>; lantiq,rcu = <&rcu0>; lantiq,rcu-endian-offset = <0x4c>; lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */ big-endian; clocks = <&pmu 32>, <&pmu 36>; clock-names = "phy", "pdi"; resets = <&reset0 12 24>, <&reset0 22 22>; reset-names = "phy", "pcie"; #phy-cells = <1>; }; ... |