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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: HiSilicon Kirin970 PCIe PHY maintainers: - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> description: |+ Bindings for PCIe PHY on HiSilicon Kirin 970. properties: compatible: const: hisilicon,hi970-pcie-phy "#phy-cells": const: 0 reg: maxItems: 1 description: PHY Control registers phy-supply: description: The PCIe PHY power supply clocks: items: - description: PCIe PHY clock - description: PCIe AUX clock - description: PCIe APB PHY clock - description: PCIe APB SYS clock - description: PCIe ACLK clock clock-names: items: - const: phy_ref - const: aux - const: apb_phy - const: apb_sys - const: aclk hisilicon,eye-diagram-param: $ref: /schemas/types.yaml#/definitions/uint32-array description: Eye diagram for phy. required: - "#phy-cells" - compatible - reg - clocks - clock-names - hisilicon,eye-diagram-param - phy-supply additionalProperties: false examples: - | #include <dt-bindings/clock/hi3670-clock.h> soc { #address-cells = <2>; #size-cells = <2>; pcie_phy: pcie-phy@fc000000 { compatible = "hisilicon,hi970-pcie-phy"; reg = <0x0 0xfc000000 0x0 0x80000>; #phy-cells = <0>; phy-supply = <&ldo33>; clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, <&crg_ctrl HI3670_ACLK_GATE_PCIE>; clock-names = "phy_ref", "aux", "apb_phy", "apb_sys", "aclk"; hisilicon,eye-diagram-param = <0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff>; }; }; |