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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek MT7981 Pin Controller maintainers: - Daniel Golle <daniel@makrotopia.org> description: The MediaTek's MT7981 Pin controller is used to control SoC pins. properties: compatible: enum: - mediatek,mt7981-pinctrl reg: minItems: 9 maxItems: 9 reg-names: items: - const: gpio - const: iocfg_rt - const: iocfg_rm - const: iocfg_rb - const: iocfg_lb - const: iocfg_bl - const: iocfg_tm - const: iocfg_tl - const: eint gpio-controller: true "#gpio-cells": const: 2 description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 description: GPIO valid number range. interrupt-controller: true interrupts: maxItems: 1 "#interrupt-cells": const: 2 allOf: - $ref: pinctrl.yaml# required: - compatible - reg - reg-names - gpio-controller - "#gpio-cells" patternProperties: '-pins$': type: object additionalProperties: false patternProperties: '^.*mux.*$': type: object additionalProperties: false description: | pinmux configuration nodes. The following table shows the effective values of "group", "function" properties and chip pinout pins groups function pins (in pin#) --------------------------------------------------------------------- "wa_aice1" "wa_aice" 0, 1 "wa_aice2" "wa_aice" 0, 1 "wm_uart_0" "uart" 0, 1 "dfd" "dfd" 0, 1, 4, 5 "watchdog" "watchdog" 2 "pcie_pereset" "pcie" 3 "jtag" "jtag" 4, 5, 6, 7, 8 "wm_jtag_0" "jtag" 4, 5, 6, 7, 8 "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13 "uart2_0" "uart" 4, 5, 6, 7 "gbe_led0" "led" 8 "pta_ext_0" "pta" 4, 5, 6 "pwm2" "pwm" 7 "net_wo0_uart_txd_0" "uart" 8 "spi1_0" "spi" 4, 5, 6, 7 "i2c0_0" "i2c" 6, 7 "dfd_ntrst" "dfd" 8 "wm_aice1" "wa_aice" 9, 10 "pwm0_0" "pwm" 13 "pwm0_1" "pwm" 15 "pwm1_0" "pwm" 14 "pwm1_1" "pwm" 15 "net_wo0_uart_txd_1" "uart" 14 "net_wo0_uart_txd_2" "uart" 15 "gbe_led1" "led" 13 "pcm" "pcm" 9, 10, 11, 12, 13, 25 "watchdog1" "watchdog" 13 "udi" "udi" 9, 10, 11, 12, 13 "drv_vbus" "usb" 14 "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 "snfi" "flash" 16, 17, 18, 19, 20, 21 "spi0" "spi" 16, 17, 18, 19 "spi0_wp_hold" "spi" 20, 21 "spi1_1" "spi" 22, 23, 24, 25 "spi2" "spi" 26, 27, 28, 29 "spi2_wp_hold" "spi" 30, 31 "uart1_0" "uart" 16, 17, 18, 19 "uart1_1" "uart" 26, 27, 28, 29 "uart2_1" "uart" 22, 23, 24, 25 "pta_ext_1" "pta" 22, 23, 24 "wm_aurt_1" "uart" 20, 21 "wm_aurt_2" "uart" 30, 31 "wm_jtag_1" "jtag" 20, 21, 22, 23, 24 "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29 "wa_aice3" "wa_aice" 28, 20 "wm_aice2" "wa_aice" 30, 31 "i2c0_1" "i2c" 30, 31 "u2_phy_i2c" "i2c" 30, 31 "uart0" "uart" 32, 33 "sgmii1_phy_i2c" "i2c" 32, 33 "u3_phy_i2c" "i2c" 32, 33 "sgmii0_phy_i2c" "i2c" 32, 33 "pcie_clk" "pcie" 34 "pcie_wake" "pcie" 35 "i2c0_2" "i2c" 36, 37 "smi_mdc_mdio" "eth" 36, 37 "gbe_ext_mdc_mdio" "eth" 36, 37 "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51 "wf2g_led0" "led" 30 "wf2g_led1" "led" 34 "wf5g_led0" "led" 31 "wf5g_led1" "led" 35 "mt7531_int" "eth" 38 "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 $ref: /schemas/pinctrl/pinmux-node.yaml properties: function: description: A string containing the name of the function to mux to the group. enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led, pwm, spi, uart, watchdog, flash, pcie] groups: description: An array of strings. Each string contains the name of a group. required: - function - groups allOf: - if: properties: function: const: wa_aice then: properties: groups: enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2] - if: properties: function: const: dfd then: properties: groups: enum: [dfd, dfd_ntrst] - if: properties: function: const: jtag then: properties: groups: enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1] - if: properties: function: const: pta then: properties: groups: enum: [pta_ext_0, pta_ext_1] - if: properties: function: const: pcm then: properties: groups: enum: [pcm] - if: properties: function: const: udi then: properties: groups: enum: [udi] - if: properties: function: const: usb then: properties: groups: enum: [drv_vbus] - if: properties: function: const: ant then: properties: groups: enum: [ant_sel] - if: properties: function: const: eth then: properties: groups: enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3, mt7531_int] - if: properties: function: const: i2c then: properties: groups: enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c, sgmii0_phy_i2c, i2c0_2] - if: properties: function: const: led then: properties: groups: enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1] - if: properties: function: const: pwm then: properties: groups: items: enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1] maxItems: 3 - if: properties: function: const: spi then: properties: groups: items: enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold] maxItems: 4 - if: properties: function: const: uart then: properties: groups: items: enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0, uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0] - if: properties: function: const: watchdog then: properties: groups: enum: [watchdog] - if: properties: function: const: flash then: properties: groups: items: enum: [emmc_45, snfi] maxItems: 1 - if: properties: function: const: pcie then: properties: groups: items: enum: [pcie_clk, pcie_wake, pcie_pereset] maxItems: 3 '^.*conf.*$': type: object additionalProperties: false description: pinconf configuration nodes. $ref: /schemas/pinctrl/pincfg-node.yaml properties: pins: description: An array of strings. Each string contains the name of a pin. items: enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N, JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10] maxItems: 57 bias-disable: true bias-pull-up: oneOf: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. bias-pull-down: oneOf: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. input-enable: true input-disable: true output-enable: true output-low: true output-high: true input-schmitt-enable: true input-schmitt-disable: true drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] mediatek,pull-up-adv: description: | Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' Pull up settings for 2 pull resistors, R0 and R1. Valid arguments are described as below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] mediatek,pull-down-adv: description: | Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' Pull down settings for 2 pull resistors, R0 and R1. Valid arguments are described as below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] required: - pins additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/mt65xx.h> soc { #address-cells = <2>; #size-cells = <2>; pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, <0 0x11c00000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d20000 0 0x1000>, <0 0x11e00000 0 0x1000>, <0 0x11e20000 0 0x1000>, <0 0x11f00000 0 0x1000>, <0 0x11f10000 0 0x1000>, <0 0x1000b000 0 0x1000>; reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 56>; interrupt-controller; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; #interrupt-cells = <2>; mdio_pins: mdio-pins { mux { function = "eth"; groups = "smi_mdc_mdio"; }; }; spi0_flash_pins: spi0-pins { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; drive-strength = <MTK_DRIVE_8mA>; bias-pull-up = <MTK_PUPD_SET_R1R0_11>; }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; drive-strength = <MTK_DRIVE_8mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_11>; }; }; pcie_pins: pcie-pins { mux { function = "pcie"; groups = "pcie_clk", "pcie_wake", "pcie_pereset"; }; }; }; }; |