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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung MIPI DSIM bridge controller maintainers: - Inki Dae <inki.dae@samsung.com> - Jagan Teki <jagan@amarulasolutions.com> - Marek Szyprowski <m.szyprowski@samsung.com> description: | Samsung MIPI DSIM bridge controller can be found it on Exynos and i.MX8M Mini/Nano/Plus SoC's. properties: compatible: oneOf: - enum: - samsung,exynos3250-mipi-dsi - samsung,exynos4210-mipi-dsi - samsung,exynos5410-mipi-dsi - samsung,exynos5422-mipi-dsi - samsung,exynos5433-mipi-dsi - fsl,imx8mm-mipi-dsim - fsl,imx8mp-mipi-dsim - items: - const: fsl,imx8mn-mipi-dsim - const: fsl,imx8mm-mipi-dsim reg: maxItems: 1 interrupts: maxItems: 1 '#address-cells': const: 1 '#size-cells': const: 0 clocks: minItems: 2 maxItems: 5 clock-names: minItems: 2 maxItems: 5 samsung,phy-type: $ref: /schemas/types.yaml#/definitions/uint32 description: phandle to the samsung phy-type power-domains: maxItems: 1 samsung,power-domain: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the associated samsung power domain vddcore-supply: description: MIPI DSIM Core voltage supply (e.g. 1.1V) vddio-supply: description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) samsung,burst-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: DSIM high speed burst mode frequency. If absent, the pixel clock from the attached device or bridge will be used instead. samsung,esc-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: DSIM escape mode frequency. samsung,pll-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: DSIM oscillator clock frequency. If absent, the clock frequency of sclk_mipi will be used instead. phys: maxItems: 1 phy-names: const: dsim ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: Input port node to receive pixel data from the display controller. Exactly one endpoint must be specified. port@1: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: DSI output port node to the panel or the next bridge in the chain. properties: endpoint: $ref: /schemas/media/video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 uniqueItems: true items: enum: [ 1, 2, 3, 4 ] lane-polarities: minItems: 1 maxItems: 5 description: The Samsung MIPI DSI IP requires that all the data lanes have the same polarity. dependencies: lane-polarities: [data-lanes] required: - clock-names - clocks - compatible - interrupts - reg - samsung,esc-clock-frequency allOf: - $ref: ../dsi-controller.yaml# - if: properties: compatible: contains: const: samsung,exynos5433-mipi-dsi then: properties: clocks: minItems: 5 clock-names: items: - const: bus_clk - const: phyclk_mipidphy0_bitclkdiv8 - const: phyclk_mipidphy0_rxclkesc0 - const: sclk_rgb_vclk_to_dsim0 - const: sclk_mipi ports: required: - port@0 required: - ports - vddcore-supply - vddio-supply - if: properties: compatible: contains: const: samsung,exynos5410-mipi-dsi then: properties: clocks: minItems: 2 clock-names: items: - const: bus_clk - const: pll_clk required: - vddcore-supply - vddio-supply - if: properties: compatible: contains: const: samsung,exynos4210-mipi-dsi then: properties: clocks: minItems: 2 clock-names: items: - const: bus_clk - const: sclk_mipi required: - vddcore-supply - vddio-supply - if: properties: compatible: contains: const: samsung,exynos3250-mipi-dsi then: properties: clocks: minItems: 2 clock-names: items: - const: bus_clk - const: pll_clk required: - vddcore-supply - vddio-supply - samsung,phy-type additionalProperties: type: object examples: - | #include <dt-bindings/clock/exynos5433.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> dsi@13900000 { compatible = "samsung,exynos5433-mipi-dsi"; reg = <0x13900000 0xC0>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&cmu_disp CLK_PCLK_DSIM0>, <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, <&cmu_disp CLK_SCLK_DSIM0>; clock-names = "bus_clk", "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", "sclk_rgb_vclk_to_dsim0", "sclk_mipi"; power-domains = <&pd_disp>; vddcore-supply = <&ldo6_reg>; vddio-supply = <&ldo7_reg>; samsung,burst-clock-frequency = <512000000>; samsung,esc-clock-frequency = <16000000>; samsung,pll-clock-frequency = <24000000>; pinctrl-names = "default"; pinctrl-0 = <&te_irq>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dsi_to_mic: endpoint { remote-endpoint = <&mic_to_dsi>; }; }; }; }; |