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2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 | // SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a774a1 SoC * * Copyright (C) 2018 Renesas Electronics Corp. */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/power/r8a774a1-sysc.h> #define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 / { compatible = "renesas,r8a774a1"; #address-cells = <2>; #size-cells = <2>; /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. * Boards that provide audio clocks should override them. */ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; opp-suspend; }; }; cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&a57_0>; }; core1 { cpu = <&a57_1>; }; }; cluster1 { core0 { cpu = <&a53_0>; }; core1 { cpu = <&a53_1>; }; core2 { cpu = <&a53_2>; }; core3 { cpu = <&a53_3>; }; }; }; a57_0: cpu@0 { compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; a57_1: cpu@1 { compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; a53_0: cpu@100 { compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <560>; }; a53_1: cpu@101 { compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <560>; }; a53_2: cpu@102 { compatible = "arm,cortex-a53"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <560>; }; a53_3: cpu@103 { compatible = "arm,cortex-a53"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <560>; }; L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A774A1_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; L2_CA53: cache-controller-1 { compatible = "cache"; power-domains = <&sysc R8A774A1_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; }; extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a57_0>, <&a57_1>; }; psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; rwdt: watchdog@e6020000 { compatible = "renesas,r8a774a1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; status = "disabled"; }; gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 16>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 912>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 29>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 911>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 15>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 910>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 16>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 909>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 18>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 908>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 26>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 907>; }; gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 906>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 906>; }; gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a774a1", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 224 4>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 905>; }; pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; }; cmt0: timer@e60f0000 { compatible = "renesas,r8a774a1-cmt0", "renesas,rcar-gen3-cmt0"; reg = <0 0xe60f0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 303>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 303>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,r8a774a1-cmt1", "renesas,rcar-gen3-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 302>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 302>; status = "disabled"; }; cmt2: timer@e6140000 { compatible = "renesas,r8a774a1-cmt1", "renesas,rcar-gen3-cmt1"; reg = <0 0xe6140000 0 0x1004>; interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 301>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 301>; status = "disabled"; }; cmt3: timer@e6148000 { compatible = "renesas,r8a774a1-cmt1", "renesas,rcar-gen3-cmt1"; reg = <0 0xe6148000 0 0x1004>; interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 300>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 300>; status = "disabled"; }; cpg: clock-controller@e6150000 { compatible = "renesas,r8a774a1-cpg-mssr"; reg = <0 0xe6150000 0 0x0bb0>; clocks = <&extal_clk>, <&extalr_clk>; clock-names = "extal", "extalr"; #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774a1-rst"; reg = <0 0xe6160000 0 0x018c>; }; sysc: system-controller@e6180000 { compatible = "renesas,r8a774a1-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; tsc: thermal@e6198000 { compatible = "renesas,r8a774a1-thermal"; reg = <0 0xe6198000 0 0x100>, <0 0xe61a0000 0 0x100>, <0 0xe61a8000 0 0x100>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 522>; #thermal-sensor-cells = <1>; }; intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 407>; }; tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 125>; status = "disabled"; }; tmu1: timer@e6fc0000 { compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 124>; status = "disabled"; }; tmu2: timer@e6fd0000 { compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 123>; status = "disabled"; }; tmu3: timer@e6fe0000 { compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 122>; status = "disabled"; }; tmu4: timer@ffc00000 { compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 121>; status = "disabled"; }; i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 931>; dmas = <&dmac1 0x91>, <&dmac1 0x90>, <&dmac2 0x91>, <&dmac2 0x90>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; i2c1: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 930>; dmas = <&dmac1 0x93>, <&dmac1 0x92>, <&dmac2 0x93>, <&dmac2 0x92>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; i2c2: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 929>; dmas = <&dmac1 0x95>, <&dmac1 0x94>, <&dmac2 0x95>, <&dmac2 0x94>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; i2c3: i2c@e66d0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 928>; dmas = <&dmac0 0x97>, <&dmac0 0x96>; dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; i2c4: i2c@e66d8000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe66d8000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 927>; dmas = <&dmac0 0x99>, <&dmac0 0x98>; dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; i2c5: i2c@e66e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe66e0000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 919>; dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; i2c6: i2c@e66e8000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a774a1", "renesas,rcar-gen3-i2c"; reg = <0 0xe66e8000 0 0x40>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 918>; dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; iic_pmic: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a774a1", "renesas,rcar-gen3-iic", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 926>; dmas = <&dmac0 0x11>, <&dmac0 0x10>; dma-names = "tx", "rx"; status = "disabled"; }; hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a774a1", "renesas,rcar-gen3-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; }; hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a774a1", "renesas,rcar-gen3-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; }; hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a774a1", "renesas,rcar-gen3-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; }; hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a774a1", "renesas,rcar-gen3-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x37>, <&dmac0 0x36>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; hscif4: serial@e66b0000 { compatible = "renesas,hscif-r8a774a1", "renesas,rcar-gen3-hscif", "renesas,hscif"; reg = <0 0xe66b0000 0 0x60>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x38>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 516>; status = "disabled"; }; hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a774a1", "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; status = "disabled"; }; usb2_clksel: clock-controller@e6590630 { compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", "renesas,rcar-gen3-usb2-clock-sel"; reg = <0 0xe6590630 0 0x02>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb_extal_clk>, <&usb3s0_clk>; clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal"; #clock-cells = <0>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; reset-names = "ehci_ohci", "hs-usb-if"; status = "disabled"; }; usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774a1-usb-dmac", "renesas,usb-dmac"; reg = <0 0xe65a0000 0 0x100>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; usb_dmac1: dma-controller@e65b0000 { compatible = "renesas,r8a774a1-usb-dmac", "renesas,usb-dmac"; reg = <0 0xe65b0000 0 0x100>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; usb3_phy0: usb-phy@e65ee000 { compatible = "renesas,r8a774a1-usb3-phy", "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal_clk>; clock-names = "usb3-if", "usb3s_clk", "usb_extal"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; }; dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a774a1", "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x10000>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7300000 { compatible = "renesas,dmac-r8a774a1", "renesas,rcar-dmac"; reg = <0 0xe7300000 0 0x10000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; }; dmac2: dma-controller@e7310000 { compatible = "renesas,dmac-r8a774a1", "renesas,rcar-dmac"; reg = <0 0xe7310000 0 0x10000>; interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; power-domains = <&sysc R8A774A1_PD_A3VC>; #iommu-cells = <1>; }; ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a774a1", "renesas,etheravb-rcar-gen3"; reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; can0: can@e6c30000 { compatible = "renesas,can-r8a774a1", "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; assigned-clock-rates = <40000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 916>; status = "disabled"; }; can1: can@e6c38000 { compatible = "renesas,can-r8a774a1", "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; assigned-clock-rates = <40000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 915>; status = "disabled"; }; canfd: can@e66c0000 { compatible = "renesas,r8a774a1-canfd", "renesas,rcar-gen3-canfd"; reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; assigned-clock-rates = <40000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; channel0 { status = "disabled"; }; channel1 { status = "disabled"; }; }; pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm1: pwm@e6e31000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm2: pwm@e6e32000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e32000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm3: pwm@e6e33000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e33000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm4: pwm@e6e34000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e34000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm5: pwm@e6e35000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e35000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pwm6: pwm@e6e36000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e36000 0 0x8>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 207>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 206>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; scif2: serial@e6e88000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e88000 0 0x40>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x13>, <&dmac1 0x12>, <&dmac2 0x13>, <&dmac2 0x12>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; scif3: serial@e6c50000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6c50000 0 0x40>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 204>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; scif4: serial@e6c40000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6c40000 0 0x40>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 203>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; scif5: serial@e6f30000 { compatible = "renesas,scif-r8a774a1", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6f30000 0 0x40>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, <&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; }; msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a774a1", "renesas,rcar-gen3-msiof"; reg = <0 0xe6e90000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 211>; dmas = <&dmac1 0x41>, <&dmac1 0x40>, <&dmac2 0x41>, <&dmac2 0x40>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 211>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof1: spi@e6ea0000 { compatible = "renesas,msiof-r8a774a1", "renesas,rcar-gen3-msiof"; reg = <0 0xe6ea0000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 210>; dmas = <&dmac1 0x43>, <&dmac1 0x42>, <&dmac2 0x43>, <&dmac2 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof2: spi@e6c00000 { compatible = "renesas,msiof-r8a774a1", "renesas,rcar-gen3-msiof"; reg = <0 0xe6c00000 0 0x0064>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 209>; dmas = <&dmac0 0x45>, <&dmac0 0x44>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 209>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof3: spi@e6c10000 { compatible = "renesas,msiof-r8a774a1", "renesas,rcar-gen3-msiof"; reg = <0 0xe6c10000 0 0x0064>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x47>, <&dmac0 0x46>; dma-names = "tx", "rx"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; vin0: video@e6ef0000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 811>; renesas,id = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin0csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin0>; }; vin0csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin0>; }; }; }; }; vin1: video@e6ef1000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 810>; renesas,id = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin1csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin1>; }; vin1csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin1>; }; }; }; }; vin2: video@e6ef2000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 809>; renesas,id = <2>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin2csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin2>; }; vin2csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin2>; }; }; }; }; vin3: video@e6ef3000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 808>; renesas,id = <3>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin3csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin3>; }; vin3csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin3>; }; }; }; }; vin4: video@e6ef4000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 807>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 807>; renesas,id = <4>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin4csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin4>; }; vin4csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin4>; }; }; }; }; vin5: video@e6ef5000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 806>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 806>; renesas,id = <5>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin5csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin5>; }; vin5csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin5>; }; }; }; }; vin6: video@e6ef6000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef6000 0 0x1000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 805>; renesas,id = <6>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin6csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin6>; }; vin6csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin6>; }; }; }; }; vin7: video@e6ef7000 { compatible = "renesas,vin-r8a774a1"; reg = <0 0xe6ef7000 0 0x1000>; interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 804>; renesas,id = <7>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; vin7csi20: endpoint@0 { reg = <0>; remote-endpoint = <&csi20vin7>; }; vin7csi40: endpoint@2 { reg = <2>; remote-endpoint = <&csi40vin7>; }; }; }; }; rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; */ /* * #clock-cells is required for audio_clkout0/1/2/3 * * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&cpg CPG_CORE R8A774A1_CLK_S0D4>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", "mix.1", "mix.0", "ctu.1", "ctu.0", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 1005>, <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, <&cpg 1015>; reset-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; rcar_sound,ctu { ctu00: ctu-0 { }; ctu01: ctu-1 { }; ctu02: ctu-2 { }; ctu03: ctu-3 { }; ctu10: ctu-4 { }; ctu11: ctu-5 { }; ctu12: ctu-6 { }; ctu13: ctu-7 { }; }; rcar_sound,dvc { dvc0: dvc-0 { dmas = <&audma1 0xbc>; dma-names = "tx"; }; dvc1: dvc-1 { dmas = <&audma1 0xbe>; dma-names = "tx"; }; }; rcar_sound,mix { mix0: mix-0 { }; mix1: mix-1 { }; }; rcar_sound,src { src0: src-0 { interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x85>, <&audma1 0x9a>; dma-names = "rx", "tx"; }; src1: src-1 { interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x87>, <&audma1 0x9c>; dma-names = "rx", "tx"; }; src2: src-2 { interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x89>, <&audma1 0x9e>; dma-names = "rx", "tx"; }; src3: src-3 { interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8b>, <&audma1 0xa0>; dma-names = "rx", "tx"; }; src4: src-4 { interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8d>, <&audma1 0xb0>; dma-names = "rx", "tx"; }; src5: src-5 { interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x8f>, <&audma1 0xb2>; dma-names = "rx", "tx"; }; src6: src-6 { interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x91>, <&audma1 0xb4>; dma-names = "rx", "tx"; }; src7: src-7 { interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x93>, <&audma1 0xb6>; dma-names = "rx", "tx"; }; src8: src-8 { interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x95>, <&audma1 0xb8>; dma-names = "rx", "tx"; }; src9: src-9 { interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x97>, <&audma1 0xba>; dma-names = "rx", "tx"; }; }; rcar_sound,ssi { ssi0: ssi-0 { interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x01>, <&audma1 0x02>; dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma1 0x04>; dma-names = "rx", "tx"; }; ssi2: ssi-2 { interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x05>, <&audma1 0x06>; dma-names = "rx", "tx"; }; ssi3: ssi-3 { interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x07>, <&audma1 0x08>; dma-names = "rx", "tx"; }; ssi4: ssi-4 { interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x09>, <&audma1 0x0a>; dma-names = "rx", "tx"; }; ssi5: ssi-5 { interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0b>, <&audma1 0x0c>; dma-names = "rx", "tx"; }; ssi6: ssi-6 { interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0d>, <&audma1 0x0e>; dma-names = "rx", "tx"; }; ssi7: ssi-7 { interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x0f>, <&audma1 0x10>; dma-names = "rx", "tx"; }; ssi8: ssi-8 { interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x11>, <&audma1 0x12>; dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x13>, <&audma1 0x14>; dma-names = "rx", "tx"; }; }; rcar_sound,ssiu { ssiu00: ssiu-0 { dmas = <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx"; }; ssiu01: ssiu-1 { dmas = <&audma0 0x35>, <&audma1 0x36>; dma-names = "rx", "tx"; }; ssiu02: ssiu-2 { dmas = <&audma0 0x37>, <&audma1 0x38>; dma-names = "rx", "tx"; }; ssiu03: ssiu-3 { dmas = <&audma0 0x47>, <&audma1 0x48>; dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { dmas = <&audma0 0x3F>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { dmas = <&audma0 0x43>, <&audma1 0x44>; dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { dmas = <&audma0 0x4F>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { dmas = <&audma0 0x53>, <&audma1 0x54>; dma-names = "rx", "tx"; }; ssiu10: ssiu-8 { dmas = <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { dmas = <&audma0 0x4B>, <&audma1 0x4C>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { dmas = <&audma0 0x57>, <&audma1 0x58>; dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { dmas = <&audma0 0x59>, <&audma1 0x5A>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { dmas = <&audma0 0x5F>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { dmas = <&audma0 0xC3>, <&audma1 0xC4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { dmas = <&audma0 0xC7>, <&audma1 0xC8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { dmas = <&audma0 0xCB>, <&audma1 0xCC>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { dmas = <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx"; }; ssiu21: ssiu-17 { dmas = <&audma0 0x67>, <&audma1 0x68>; dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { dmas = <&audma0 0x6B>, <&audma1 0x6C>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { dmas = <&audma0 0x6D>, <&audma1 0x6E>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { dmas = <&audma0 0xCF>, <&audma1 0xCE>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { dmas = <&audma0 0xEB>, <&audma1 0xEC>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { dmas = <&audma0 0xED>, <&audma1 0xEE>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { dmas = <&audma0 0xEF>, <&audma1 0xF0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { dmas = <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx"; }; ssiu31: ssiu-25 { dmas = <&audma0 0x21>, <&audma1 0x22>; dma-names = "rx", "tx"; }; ssiu32: ssiu-26 { dmas = <&audma0 0x23>, <&audma1 0x24>; dma-names = "rx", "tx"; }; ssiu33: ssiu-27 { dmas = <&audma0 0x25>, <&audma1 0x26>; dma-names = "rx", "tx"; }; ssiu34: ssiu-28 { dmas = <&audma0 0x27>, <&audma1 0x28>; dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { dmas = <&audma0 0x29>, <&audma1 0x2A>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { dmas = <&audma0 0x2B>, <&audma1 0x2C>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { dmas = <&audma0 0x2D>, <&audma1 0x2E>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { dmas = <&audma0 0x17>, <&audma1 0x18>; dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { dmas = <&audma0 0x19>, <&audma1 0x1A>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { dmas = <&audma0 0x1B>, <&audma1 0x1C>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { dmas = <&audma0 0x1D>, <&audma1 0x1E>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { dmas = <&audma0 0x1F>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { dmas = <&audma0 0x31>, <&audma1 0x32>; dma-names = "rx", "tx"; }; ssiu47: ssiu-39 { dmas = <&audma0 0x33>, <&audma1 0x34>; dma-names = "rx", "tx"; }; ssiu50: ssiu-40 { dmas = <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx"; }; ssiu60: ssiu-41 { dmas = <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx"; }; ssiu70: ssiu-42 { dmas = <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx"; }; ssiu80: ssiu-43 { dmas = <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx"; }; ssiu90: ssiu-44 { dmas = <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { dmas = <&audma0 0x7F>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { dmas = <&audma0 0x81>, <&audma1 0x82>; dma-names = "rx", "tx"; }; ssiu93: ssiu-47 { dmas = <&audma0 0x83>, <&audma1 0x84>; dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { dmas = <&audma0 0xA3>, <&audma1 0xA4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { dmas = <&audma0 0xA5>, <&audma1 0xA6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { dmas = <&audma0 0xA7>, <&audma1 0xA8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { dmas = <&audma0 0xA9>, <&audma1 0xAA>; dma-names = "rx", "tx"; }; }; }; audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a774a1", "renesas,rcar-dmac"; reg = <0 0xec700000 0 0x10000>; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, <&ipmmu_mp 2>, <&ipmmu_mp 3>, <&ipmmu_mp 4>, <&ipmmu_mp 5>, <&ipmmu_mp 6>, <&ipmmu_mp 7>, <&ipmmu_mp 8>, <&ipmmu_mp 9>, <&ipmmu_mp 10>, <&ipmmu_mp 11>, <&ipmmu_mp 12>, <&ipmmu_mp 13>, <&ipmmu_mp 14>, <&ipmmu_mp 15>; }; audma1: dma-controller@ec720000 { compatible = "renesas,dmac-r8a774a1", "renesas,rcar-dmac"; reg = <0 0xec720000 0 0x10000>; interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, <&ipmmu_mp 18>, <&ipmmu_mp 19>, <&ipmmu_mp 20>, <&ipmmu_mp 21>, <&ipmmu_mp 22>, <&ipmmu_mp 23>, <&ipmmu_mp 24>, <&ipmmu_mp 25>, <&ipmmu_mp 26>, <&ipmmu_mp 27>, <&ipmmu_mp 28>, <&ipmmu_mp 29>, <&ipmmu_mp 30>, <&ipmmu_mp 31>; }; xhci0: usb@ee000000 { compatible = "renesas,xhci-r8a774a1", "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; usb3_peri0: usb@ee020000 { compatible = "renesas,r8a774a1-usb3-peri", "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; status = "disabled"; }; ohci1: usb@ee0a0000 { compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; phys = <&usb2_phy1 1>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; ehci0: usb@ee080100 { compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; status = "disabled"; }; ehci1: usb@ee0a0100 { compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; usb2_phy0: usb-phy@ee080200 { compatible = "renesas,usb2-phy-r8a774a1", "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; #phy-cells = <1>; status = "disabled"; }; usb2_phy1: usb-phy@ee0a0200 { compatible = "renesas,usb2-phy-r8a774a1", "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 702>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; #phy-cells = <1>; status = "disabled"; }; sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; status = "disabled"; }; sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; status = "disabled"; }; sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; status = "disabled"; }; sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; status = "disabled"; }; rpc: spi@ee200000 { compatible = "renesas,r8a774a1-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>, <0 0xee208000 0 0x100>; reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x20000>, <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 408>; }; pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a774a1", "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; device_type = "pci"; ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; /* Map all possible DDR/IOMMU as inbound ranges */ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 319>; iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; }; pciec1: pcie@ee800000 { compatible = "renesas,pcie-r8a774a1", "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; device_type = "pci"; ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; /* Map all possible DDR/IOMMU as inbound ranges */ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 318>; iommu-map = <0 &ipmmu_hc 1 1>; iommu-map-mask = <0>; status = "disabled"; }; pciec0_ep: pcie-ep@fe000000 { compatible = "renesas,r8a774a1-pcie-ep", "renesas,rcar-gen3-pcie-ep"; reg = <0x0 0xfe000000 0 0x80000>, <0x0 0xfe100000 0 0x100000>, <0x0 0xfe200000 0 0x200000>, <0x0 0x30000000 0 0x8000000>, <0x0 0x38000000 0 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 319>; clock-names = "pcie"; resets = <&cpg 319>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; pciec1_ep: pcie-ep@ee800000 { compatible = "renesas,r8a774a1-pcie-ep", "renesas,rcar-gen3-pcie-ep"; reg = <0x0 0xee800000 0 0x80000>, <0x0 0xee900000 0 0x100000>, <0x0 0xeea00000 0 0x200000>, <0x0 0xc0000000 0 0x8000000>, <0x0 0xc8000000 0 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 318>; clock-names = "pcie"; resets = <&cpg 318>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 119>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 119>; renesas,fcp = <&fcpf0>; }; fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; clocks = <&cpg CPG_MOD 615>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 615>; }; fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; clocks = <&cpg CPG_MOD 607>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 607>; }; fcpvd0: fcp@fea27000 { compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; clocks = <&cpg CPG_MOD 603>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 603>; iommus = <&ipmmu_vi0 8>; }; fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 602>; iommus = <&ipmmu_vi0 9>; }; fcpvd2: fcp@fea37000 { compatible = "renesas,fcpv"; reg = <0 0xfea37000 0 0x200>; clocks = <&cpg CPG_MOD 601>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 601>; iommus = <&ipmmu_vi0 10>; }; fcpvi0: fcp@fe9af000 { compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; clocks = <&cpg CPG_MOD 611>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 611>; iommus = <&ipmmu_vc0 19>; }; vspb: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 626>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 626>; renesas,fcp = <&fcpvb0>; }; vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 623>; renesas,fcp = <&fcpvd0>; }; vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 622>; renesas,fcp = <&fcpvd1>; }; vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; reg = <0 0xfea30000 0 0x5000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 621>; renesas,fcp = <&fcpvd2>; }; vspi0: vsp@fe9a0000 { compatible = "renesas,vsp2"; reg = <0 0xfe9a0000 0 0x8000>; interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 631>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 631>; renesas,fcp = <&fcpvi0>; }; csi20: csi2@fea80000 { compatible = "renesas,r8a774a1-csi2"; reg = <0 0xfea80000 0 0x10000>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 714>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 714>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; csi20vin0: endpoint@0 { reg = <0>; remote-endpoint = <&vin0csi20>; }; csi20vin1: endpoint@1 { reg = <1>; remote-endpoint = <&vin1csi20>; }; csi20vin2: endpoint@2 { reg = <2>; remote-endpoint = <&vin2csi20>; }; csi20vin3: endpoint@3 { reg = <3>; remote-endpoint = <&vin3csi20>; }; csi20vin4: endpoint@4 { reg = <4>; remote-endpoint = <&vin4csi20>; }; csi20vin5: endpoint@5 { reg = <5>; remote-endpoint = <&vin5csi20>; }; csi20vin6: endpoint@6 { reg = <6>; remote-endpoint = <&vin6csi20>; }; csi20vin7: endpoint@7 { reg = <7>; remote-endpoint = <&vin7csi20>; }; }; }; }; csi40: csi2@feaa0000 { compatible = "renesas,r8a774a1-csi2"; reg = <0 0xfeaa0000 0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 716>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 716>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; csi40vin0: endpoint@0 { reg = <0>; remote-endpoint = <&vin0csi40>; }; csi40vin1: endpoint@1 { reg = <1>; remote-endpoint = <&vin1csi40>; }; csi40vin2: endpoint@2 { reg = <2>; remote-endpoint = <&vin2csi40>; }; csi40vin3: endpoint@3 { reg = <3>; remote-endpoint = <&vin3csi40>; }; csi40vin4: endpoint@4 { reg = <4>; remote-endpoint = <&vin4csi40>; }; csi40vin5: endpoint@5 { reg = <5>; remote-endpoint = <&vin5csi40>; }; csi40vin6: endpoint@6 { reg = <6>; remote-endpoint = <&vin6csi40>; }; csi40vin7: endpoint@7 { reg = <7>; remote-endpoint = <&vin7csi40>; }; }; }; }; hdmi0: hdmi@fead0000 { compatible = "renesas,r8a774a1-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A774A1_CLK_HDMI>; clock-names = "iahb", "isfr"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 729>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dw_hdmi0_in: endpoint { remote-endpoint = <&du_out_hdmi0>; }; }; port@1 { reg = <1>; }; port@2 { /* HDMI sound */ reg = <2>; }; }; }; du: display@feb00000 { compatible = "renesas,du-r8a774a1"; reg = <0 0xfeb00000 0 0x70000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>; clock-names = "du.0", "du.1", "du.2"; resets = <&cpg 724>, <&cpg 722>; reset-names = "du.0", "du.2"; status = "disabled"; renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; du_out_hdmi0: endpoint { remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { reg = <2>; du_out_lvds0: endpoint { remote-endpoint = <&lvds0_in>; }; }; }; }; lvds0: lvds@feb90000 { compatible = "renesas,r8a774a1-lvds"; reg = <0 0xfeb90000 0 0x14>; clocks = <&cpg CPG_MOD 727>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 727>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; lvds0_in: endpoint { remote-endpoint = <&du_out_lvds0>; }; }; port@1 { reg = <1>; }; }; }; prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; }; thermal-zones { sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; sustainable-power = <3874>; trips { sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; sustainable-power = <3874>; trips { sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; sustainable-power = <3874>; cooling-maps { map0 { trip = <&target>; cooling-device = <&a57_0 0 2>; contribution = <1024>; }; map1 { trip = <&target>; cooling-device = <&a53_0 0 2>; contribution = <1024>; }; }; trips { target: trip-point1 { temperature = <100000>; hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; }; |