# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Resizer

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  One of Media Data Path 3 (MDP3) components used to do frame resizing.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8183-mdp3-rsz

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  clocks:
    minItems: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>

    mdp3_rsz0: mdp3-rsz0@14003000 {
      compatible = "mediatek,mt8183-mdp3-rsz";
      reg = <0x14003000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
    };

    mdp3_rsz1: mdp3-rsz1@14004000 {
      compatible = "mediatek,mt8183-mdp3-rsz";
      reg = <0x14004000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
    };