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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive JH7100 Pin Controller description: | Bindings for the JH7100 RISC-V SoC from StarFive Ltd. Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63] and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have configurable bias, drive strength, schmitt trigger etc. The SoC has an interesting 2-layered approach to pin muxing best illustrated by the diagram below. Signal group 0, 1, ... or 6 ___|___ | | LCD output -----------------| | CMOS Camera interface ------| |--- PAD_GPIO[0] Ethernet PHY interface -----| MUX |--- PAD_GPIO[1] ... | | ... | |--- PAD_GPIO[63] -------- GPIO0 ------------| | | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0] | | | | | |--- PAD_FUNC_SHARE[1] | | | | ... | | ... | | | | | |--- PAD_FUNC_SHARE[141] | | -----|---|-- GPIO63 ---| | | | | | | | ------- UART0 UART1 -- The big MUX in the diagram only has 7 different ways of mapping peripherals on the left to pins on the right. StarFive calls the 7 configurations "signal groups". However some peripherals have their I/O go through the 64 "GPIOs". The diagram only shows UART0 and UART1, but this also includes a number of other UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64 GPIOs such that any GPIO can be set up to be controlled by any of the peripherals. Note that signal group 0 doesn't map any of the GPIOs to pins, and only signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63]. maintainers: - Emil Renner Berthing <kernel@esmil.dk> - Drew Fustini <drew@beagleboard.org> properties: compatible: const: starfive,jh7100-pinctrl reg: minItems: 2 maxItems: 2 reg-names: items: - const: gpio - const: padctl clocks: maxItems: 1 resets: maxItems: 1 gpio-controller: true "#gpio-cells": const: 2 interrupts: maxItems: 1 description: The GPIO parent interrupt. interrupt-controller: true "#interrupt-cells": const: 2 starfive,signal-group: description: | Select one of the 7 signal groups. If this property is not set it defaults to the configuration already chosen by the earlier boot stages. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6] required: - compatible - reg - reg-names - clocks - gpio-controller - "#gpio-cells" - interrupts - interrupt-controller - "#interrupt-cells" patternProperties: '-[0-9]+$': type: object patternProperties: '-pins$': type: object description: | A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, bias, input enable/disable, input schmitt trigger enable/disable, slew-rate and drive strength. $ref: /schemas/pinctrl/pincfg-node.yaml properties: pins: description: | The list of pin identifiers that properties in the node apply to. This should be set using either the PAD_GPIO or PAD_FUNC_SHARE macros. Either this or "pinmux" has to be specified, but not both. $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins pinmux: description: | The list of GPIOs and their mux settings that properties in the node apply to. This should be set using the GPIOMUX macro. Either this or "pins" has to be specified, but not both. $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux bias-disable: true bias-pull-up: type: boolean bias-pull-down: type: boolean drive-strength: enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ] input-enable: true input-disable: true input-schmitt-enable: true input-schmitt-disable: true slew-rate: maximum: 7 starfive,strong-pull-up: description: enable strong pull-up. type: boolean additionalProperties: false additionalProperties: false additionalProperties: false examples: - | #include <dt-bindings/clock/starfive-jh7100.h> #include <dt-bindings/reset/starfive-jh7100.h> #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> soc { #address-cells = <2>; #size-cells = <2>; pinctrl@11910000 { compatible = "starfive,jh7100-pinctrl"; reg = <0x0 0x11910000 0x0 0x10000>, <0x0 0x11858000 0x0 0x1000>; reg-names = "gpio", "padctl"; clocks = <&clkgen JH7100_CLK_GPIO_APB>; resets = <&clkgen JH7100_RSTN_GPIO_APB>; interrupts = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; starfive,signal-group = <6>; gmac_pins_default: gmac-0 { gtxclk-pins { pins = <PAD_FUNC_SHARE(115)>; bias-pull-up; drive-strength = <35>; input-enable; input-schmitt-enable; slew-rate = <0>; }; miitxclk-pins { pins = <PAD_FUNC_SHARE(116)>; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <0>; }; tx-pins { pins = <PAD_FUNC_SHARE(117)>, <PAD_FUNC_SHARE(119)>, <PAD_FUNC_SHARE(120)>, <PAD_FUNC_SHARE(121)>, <PAD_FUNC_SHARE(122)>, <PAD_FUNC_SHARE(123)>, <PAD_FUNC_SHARE(124)>, <PAD_FUNC_SHARE(125)>, <PAD_FUNC_SHARE(126)>; bias-disable; drive-strength = <35>; input-disable; input-schmitt-disable; slew-rate = <0>; }; rxclk-pins { pins = <PAD_FUNC_SHARE(127)>; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <6>; }; rxer-pins { pins = <PAD_FUNC_SHARE(129)>; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <0>; }; rx-pins { pins = <PAD_FUNC_SHARE(128)>, <PAD_FUNC_SHARE(130)>, <PAD_FUNC_SHARE(131)>, <PAD_FUNC_SHARE(132)>, <PAD_FUNC_SHARE(133)>, <PAD_FUNC_SHARE(134)>, <PAD_FUNC_SHARE(135)>, <PAD_FUNC_SHARE(136)>, <PAD_FUNC_SHARE(137)>, <PAD_FUNC_SHARE(138)>, <PAD_FUNC_SHARE(139)>, <PAD_FUNC_SHARE(140)>, <PAD_FUNC_SHARE(141)>; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-enable; slew-rate = <0>; }; }; i2c0_pins_default: i2c0-0 { i2c-pins { pinmux = <GPIOMUX(62, GPO_LOW, GPO_I2C0_PAD_SCK_OEN, GPI_I2C0_PAD_SCK_IN)>, <GPIOMUX(61, GPO_LOW, GPO_I2C0_PAD_SDA_OEN, GPI_I2C0_PAD_SDA_IN)>; bias-disable; /* external pull-up */ input-enable; input-schmitt-enable; }; }; uart3_pins_default: uart3-0 { rx-pins { pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, GPI_UART3_PAD_SIN)>; bias-pull-up; input-enable; input-schmitt-enable; }; tx-pins { pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT, GPO_ENABLE, GPI_NONE)>; bias-disable; input-disable; input-schmitt-disable; }; }; }; gmac { pinctrl-0 = <&gmac_pins_default>; pinctrl-names = "default"; }; i2c { pinctrl-0 = <&i2c0_pins_default>; pinctrl-names = "default"; }; uart3 { pinctrl-0 = <&uart3_pins_default>; pinctrl-names = "default"; }; }; ... |