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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2019 NXP * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> */ /dts-v1/; #include "imx8mp-debix-som-a.dtsi" / { model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; aliases { ethernet0 = &eqos; ethernet1 = &fec; }; chosen { stdout-path = &uart2; }; reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "BB_VDD3V3"; /* Required timings for ethernet phy's */ startup-delay-us = <50000>; off-on-delay-us = <110000>; gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "BB_VDD5V"; gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; regulator-som-vdd1v8 { compatible = "regulator-fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-name = "SOM_VDD1V8_SW"; gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; regulator-som-vdd3v3 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "SOM_VDD3V3_SW"; gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; regulator-vbus-usb20 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "USB20_5V"; gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; vin-supply = <®_baseboard_vdd5v0>; }; regulator-vbus-usb30 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "USB30_5V"; gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; vin-supply = <®_baseboard_vdd5v0>; }; reg_vdd5v0: regulator-vdd5v0 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "VDD_5V"; gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; nvmem-cells = <ðmac1>; nvmem-cell-names = "mac-address"; phy-supply = <®_baseboard_vdd3v3>; phy-handle = <ðphy0>; phy-mode = "rgmii-id"; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; reset-assert-us = <20000>; reset-deassert-us = <150000>; eee-broken-1000t; realtek,clkout-disable; }; }; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; nvmem-cells = <ðmac2>; nvmem-cell-names = "mac-address"; phy-supply = <®_baseboard_vdd3v3>; phy-handle = <ðphy1>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; reset-assert-us = <20000>; reset-deassert-us = <150000>; eee-broken-1000t; realtek,clkout-disable; }; }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_vdd5v0>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_vdd5v0>; status = "okay"; }; &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; status = "okay"; flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; }; }; &i2c4 { expander0: gpio@20 { compatible = "nxp,pca9535"; reg = <0x20>; gpio-controller; #gpio-cells = <0x02>; }; expander1: gpio@23 { compatible = "nxp,pca9535"; reg = <0x23>; gpio-controller; #gpio-cells = <0x02>; /* * Since USB1 is bound to peripheral mode we need to ensure * that VBUS is turned off. */ usb30-otg-hog { gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>; output-low; line-name = "USB30_OTG_EN"; }; }; rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupt-parent = <&gpio4>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; #clock-cells = <0>; }; eeprom@52 { compatible = "atmel,24c02"; reg = <0x52>; pagesize = <16>; #address-cells = <1>; #size-cells = <0>; /* MACs stored in ASCII */ ethmac1: mac-address@0 { reg = <0x0 0xc>; }; ethmac2: mac-address@c { reg = <0xc 0xc>; }; }; }; &snvs_pwrkey { status = "okay"; }; /* Debug */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; &usb3_0 { status = "okay"; }; &usb3_1 { status = "okay"; }; &usb_dwc3_0 { dr_mode = "peripheral"; status = "okay"; }; &usb_dwc3_1 { dr_mode = "host"; #address-cells = <1>; #size-cells = <0>; status = "okay"; /* 2.x hub on port 1 */ usb_hub_2_x: hub@1 { compatible = "usb5e3,610"; reg = <1>; reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; vdd-supply = <®_vdd5v0>; peer-hub = <&usb_hub_3_x>; }; /* 3.x hub on port 2 */ usb_hub_3_x: hub@2 { compatible = "usb5e3,620"; reg = <2>; reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; vdd-supply = <®_vdd5v0>; peer-hub = <&usb_hub_2_x>; }; }; &usb3_phy0 { status = "okay"; }; &usb3_phy1 { status = "okay"; }; /* µSD Card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>; assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; disable-wp; no-sdio; no-mmc; status = "okay"; }; &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 >; }; pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 >; }; pinctrl_rtc: rtcgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 >; }; pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 >; }; pinctrl_uart4: uart4grp { fsl,pins = < MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; }; |