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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 | * Freescale Management Complex The Freescale Management Complex (fsl-mc) is a hardware resource manager that manages specialized hardware objects used in network-oriented packet processing applications. After the fsl-mc block is enabled, pools of hardware resources are available, such as queues, buffer pools, I/O interfaces. These resources are building blocks that can be used to create functional hardware objects/devices such as network interfaces, crypto accelerator instances, L2 switches, etc. For an overview of the DPAA2 architecture and fsl-mc bus see: Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst As described in the above overview, all DPAA2 objects in a DPRC share the same hardware "isolation context" and a 10-bit value called an ICID (isolation context id) is expressed by the hardware to identify the requester. The generic 'iommus' property is insufficient to describe the relationship between ICIDs and IOMMUs, so an iommu-map property is used to define the set of possible ICIDs under a root DPRC and how they map to an IOMMU. For generic IOMMU bindings, see Documentation/devicetree/bindings/iommu/iommu.txt. For arm-smmu binding, see: Documentation/devicetree/bindings/iommu/arm,smmu.yaml. The MSI writes are accompanied by sideband data which is derived from the ICID. The msi-map property is used to associate the devices with both the ITS controller and the sideband data which accompanies the writes. For generic MSI bindings, see Documentation/devicetree/bindings/interrupt-controller/msi.txt. For GICv3 and GIC ITS bindings, see: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. Required properties: - compatible Value type: <string> Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex compatible with this binding must have Block Revision Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in the MC control register region. - reg Value type: <prop-encoded-array> Definition: A standard property. Specifies one or two regions defining the MC's registers: -the first region is the command portal for the this machine and must always be present -the second region is the MC control registers. This region may not be present in some scenarios, such as in the device tree presented to a virtual machine. - ranges Value type: <prop-encoded-array> Definition: A standard property. Defines the mapping between the child MC address space and the parent system address space. The MC address space is defined by 3 components: <region type> <offset hi> <offset lo> Valid values for region type are 0x0 - MC portals 0x1 - QBMAN portals - #address-cells Value type: <u32> Definition: Must be 3. (see definition in 'ranges' property) - #size-cells Value type: <u32> Definition: Must be 1. Sub-nodes: The fsl-mc node may optionally have dpmac sub-nodes that describe the relationship between the Ethernet MACs which belong to the MC and the Ethernet PHYs on the system board. The dpmac nodes must be under a node named "dpmacs" which contains the following properties: - #address-cells Value type: <u32> Definition: Must be present if dpmac sub-nodes are defined and must have a value of 1. - #size-cells Value type: <u32> Definition: Must be present if dpmac sub-nodes are defined and must have a value of 0. These nodes must have the following properties: - compatible Value type: <string> Definition: Must be "fsl,qoriq-mc-dpmac". - reg Value type: <prop-encoded-array> Definition: Specifies the id of the dpmac. - phy-handle Value type: <phandle> Definition: Specifies the phandle to the PHY device node associated with the this dpmac. Optional properties: - iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier data. The property is an arbitrary number of tuples of (icid-base,iommu,iommu-base,length). Any ICID i in the interval [icid-base, icid-base + length) is associated with the listed IOMMU, with the iommu-specifier (i - icid-base + iommu-base). - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier data. The property is an arbitrary number of tuples of (icid-base,gic-its,msi-base,length). Any ICID in the interval [icid-base, icid-base + length) is associated with the listed GIC ITS, with the msi-specifier (i - icid-base + msi-base). Deprecated properties: - msi-parent Value type: <phandle> Definition: Describes the MSI controller node handling message interrupts for the MC. When there is no translation between the ICID and deviceID this property can be used to describe the MSI controller used by the devices on the mc-bus. The use of this property for mc-bus is deprecated. Please use msi-map. Example: smmu: iommu@5000000 { compatible = "arm,mmu-500"; #iommu-cells = <1>; stream-match-mask = <0x7C00>; ... }; gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; ... } its: gic-its@6020000 { compatible = "arm,gic-v3-its"; msi-controller; ... }; fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ /* define map for ICIDs 23-64 */ iommu-map = <23 &smmu 23 41>; /* define msi map for ICIDs 23-64 */ msi-map = <23 &its 23 41>; #address-cells = <3>; #size-cells = <1>; /* * Region type 0x0 - MC portals * Region type 0x1 - QBMAN portals */ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; dpmacs { #address-cells = <1>; #size-cells = <0>; dpmac@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; phy-handle = <&mdio0_phy0>; } } }; |