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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 | // SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (C) 2021 StarFive Technology Co., Ltd. * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> */ /dts-v1/; #include <dt-bindings/clock/starfive-jh7100.h> #include <dt-bindings/reset/starfive-jh7100.h> / { compatible = "starfive,jh7100"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; U74_0: cpu@0 { compatible = "sifive,u74-mc", "riscv"; reg = <0>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <32>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; tlb-split; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; U74_1: cpu@1 { compatible = "sifive,u74-mc", "riscv"; reg = <1>; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; d-tlb-sets = <1>; d-tlb-size = <32>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; tlb-split; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; cpu-map { cluster0 { core0 { cpu = <&U74_0>; }; core1 { cpu = <&U74_1>; }; }; }; }; thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <15000>; thermal-sensors = <&sfctemp>; trips { cpu_alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; cpu_crit { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "critical"; }; }; }; }; osc_sys: osc_sys { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; osc_aud: osc_aud { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; gmac_rmii_ref: gmac_rmii_ref { compatible = "fixed-clock"; #clock-cells = <0>; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { compatible = "fixed-clock"; #clock-cells = <0>; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; soc { compatible = "simple-bus"; interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; ranges; clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>; }; plic: interrupt-controller@c000000 { compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 &cpu1_intc 11 &cpu1_intc 9>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; riscv,ndev = <133>; }; clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; #clock-cells = <1>; }; rstgen: reset-controller@11840000 { compatible = "starfive,jh7100-reset"; reg = <0x0 0x11840000 0x0 0x10000>; #reset-cells = <1>; }; i2c0: i2c@118b0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118b0000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_I2C0_CORE>, <&clkgen JH7100_CLK_I2C0_APB>; clock-names = "ref", "pclk"; resets = <&rstgen JH7100_RSTN_I2C0_APB>; interrupts = <96>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@118c0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118c0000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_I2C1_CORE>, <&clkgen JH7100_CLK_I2C1_APB>; clock-names = "ref", "pclk"; resets = <&rstgen JH7100_RSTN_I2C1_APB>; interrupts = <97>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; gpio: pinctrl@11910000 { compatible = "starfive,jh7100-pinctrl"; reg = <0x0 0x11910000 0x0 0x10000>, <0x0 0x11858000 0x0 0x1000>; reg-names = "gpio", "padctl"; clocks = <&clkgen JH7100_CLK_GPIO_APB>; resets = <&rstgen JH7100_RSTN_GPIO_APB>; interrupts = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; uart2: serial@12430000 { compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; reg = <0x0 0x12430000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_UART2_CORE>, <&clkgen JH7100_CLK_UART2_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen JH7100_RSTN_UART2_APB>; interrupts = <72>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; uart3: serial@12440000 { compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; reg = <0x0 0x12440000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_UART3_CORE>, <&clkgen JH7100_CLK_UART3_APB>; clock-names = "baudclk", "apb_pclk"; resets = <&rstgen JH7100_RSTN_UART3_APB>; interrupts = <73>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; i2c2: i2c@12450000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12450000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_I2C2_CORE>, <&clkgen JH7100_CLK_I2C2_APB>; clock-names = "ref", "pclk"; resets = <&rstgen JH7100_RSTN_I2C2_APB>; interrupts = <74>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@12460000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12460000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_I2C3_CORE>, <&clkgen JH7100_CLK_I2C3_APB>; clock-names = "ref", "pclk"; resets = <&rstgen JH7100_RSTN_I2C3_APB>; interrupts = <75>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; watchdog@12480000 { compatible = "starfive,jh7100-wdt"; reg = <0x0 0x12480000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, <&clkgen JH7100_CLK_WDT_CORE>; clock-names = "apb", "core"; resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, <&rstgen JH7100_RSTN_WDT>; }; sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>; clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, <&clkgen JH7100_CLK_TEMP_APB>; clock-names = "sense", "bus"; resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, <&rstgen JH7100_RSTN_TEMP_APB>; reset-names = "sense", "bus"; #thermal-sensor-cells = <0>; }; }; }; |